/bbs/pub/vlog-synth By Subject
- J. Bhasker (Fri Oct 05 2001 - 07:04:01 PDT)
- ! vs. ~
- (* synthesis, keep [=<optional_value>] *)
- (* synthesis, keep [=<optional_value>] *) // ALL?
- (no subject)
- 1364.1 ballot responses
- 1364.1 comments
- 1364.1 draft 1.8
- 1364.1 in ballot
- 1364.1 passes second recirculation ballot
- 1364.1 pragmas
- 1364.1 recirculation ballot
- 1364.1 Semantics Section 4.
- 1364.1 v2.1 draft COMMENTS
- 1364.1 Verilog Synthesis Working Group Meeting
- 1364.1 Verilog Synthesis Working Group Meeting: REMINDER
- 1364.1 WG meeting at HDLCON
- 1364.1 working group policy
- 1364.1: ROM and RAM modeling
- 5.4 Modeling three-state drivers
- 6.1 Synthesis attributes // minor syntax update
- 6.3.2
- [Fwd: BOUNCE vlog-synth@eda.org: Non-member submission from[Daryl.Stewart@tenisontech.com]]
- [Fwd: Exemplar Handling of Initial Statement]
- [Fwd: Final Call for Papers, NOTE 9/22/00 deadline extension]
- [Fwd: JOURNAL OF SYSTEMS ARCHITECTURE, Final Call For Papers]
- [Fwd: Some comments on IEEE P1364.1/D1.7]
- [vlog-synth] [Fwd: Last Call for Papers - EDP 2004 - Design Process Workshop]
- [vlog-synth] Call for Contributions FDL 2003
- [vlog-synth] Dersigning FSM
- [vlog-synth] DVCon 2004 Call For Papers
- [vlog-synth] FDL'03
- [vlog-synth] Hey, dude, it's me ^_^ :P
- [vlog-synth] Signed Multiplier generation
- [vlog-synth] This is a test message - please ignore.
- [vlog-synth] Verilog 2005
- `celldefine issue: Verilog RTL synthesis subset
- Agenda for tomorrow tele-conference
- Annex B Replacement Proposal
- Another attribute: test_port
- assigning 'X'
- Assigning / testing different sizes -- shouldn't we restrict the use?
- Assignments in the Verilog RTL Synthesizes draft
- Asynchronous design
- Attribute "encoding"
- Attribute KEEP vs NO_DUPLICATE & "clock uncertainty".
- attribute: test_port // more comments
- attribute: test_port // new text proposal
- attributes
- Attributes & Synthesis Pragmas
- Attributes and constant expressions
- Awards for standards activities
- Back online
- Ballot comment: multiplication
- Ballot feedback: test_port
- Ballot response document
- Blackbox attribute
- BNR draft items
- BTF Conference Call - Verilog Attributes & Pragmas Discussion
- Cadence (Ambit) pragmas
- Call for DASC WG Nominations
- Call for Papers IEEE/DATC EDP '99
- case-generate grammar issues.
- Comments on 1364.1 D1.4
- Comments on P1364.1/Draft 2.3
- Comments on P1364.1/Draft 2.3, Clause 5
- Comments on P1364.1/Draft 2.3, Clause 6
- Compilation pragmas
- Con Call MInutes, July 6, 2001
- Conference Call Minutes, Aug 10, 2001
- constant function
- correction in my earlier email.
- correction to section 5.4
- Critical need for HW design engineers
- D1_7 Pragmas Proposal - Section 6 - (updated 20011206)
- D1_7 Pragmas Proposal - Section 6 - 20011025
- DASC & SA Fees?
- DASC member
- DASC: draft procedures on web site
- DATE'99 Call for papers
- DDECS 2000 Call For Papers
- draft 1.3
- Draft 1.4 Verilog RTL synthesis
- Draft 1.9 // synthesis encoding vs state_machine
- Draft D2.2 for ballot
- Draft Proposal: 5.6 Modeling Read-Only Memories (ROM); 5.7 RAM
- DSD2000 Symposium, First Call for Papers
- e-mail address
- Edge-sensitive sequential logic
- Editor
- Editorial coordination on draft 1364.1
- Electronic Standards Delivery Issue
- EUROMICRO'99 DSD Workshop
- EUROMICRO'99 DSD Workshop, Call for Papers
- EUROMICRO'99: DSD Workshop - Last Call for Papers
- example may be improved...
- FDL 2001 Advance Program Announcement
- FDL conference
- FDL'98 Invitation
- FDL'99 Call for Contributions
- feedback for the ballot response document
- Floating point synthesis, call for participation
- For page 64, Section 4, example 4.4.3 -- value can't be verified
- FSM Enhancement Goals and Thoughts
- full_case, parallel_case
- fullcase/parallel case (fwd)
- function semantics
- Functional Mismatches
- Functional Mismatches Paper on the vlog-synth Web Site
- Fwd: Implicit FSMs style with mutiple clocks
- Fwd: Proposal for ROM and RAM modeling Styles
- FYI: Initialization of RAM
- Generate & defparams in Vlog-2001.
- HDL Con Paper
- HDL Con Paper:
- HDLCon 2002 Call for Papers
- Here we go again ...
- Hierarchical names: Verilog RTL synthesis
- IEEE approves PAR for Verilog Synthesis subset
- IEEE Fees??
- IEEE Std 1076.6-2004 and IEEE Std 1364.1-2002
- Implicit FSMs style with mutiple clocks
- Incomplete Sensitivity Lists
- Inferring FPGA Hardware Features?
- Inferring FPGA Hardware Features?t
- Inferring RAMs in Verilog
- Inferring ROMs in Verilog
- Initial Blocks fail with Synopsys Tools
- International HDL Conference 2000 CALL FOR PAPERS
- Invitation to Ballot for P1364.1
- JASS Journal - Call for Papers
- Keep Attribute // An update
- Looking for peace in the VHDL and Verilog Attributes
- LRM 5.x: Unclear about when block refires on same event that changed
- Making ballot responses consistent
- Meeting minutes - Verilog Synthesis Working Group Meeting: Sept 7, 2001
- Meeting Minutes: 1364.1 Verilog Synthesis Working Group Meeting
- Meeting Minutes: P1364.1 Verilog Synthesis WG
- Meeting Minutes: Verilog Synthesis Interoperability Working Group Meeting on Nov 2, '01
- Meetings schedule, 1364.1
- Minor corrections to IEEE P1364.1 / D1.7
- Minutes, Teleconference, Aug 4, 1998
- Mismatch Paper PDF File - 2nd try
- Modelling of level sensitive devices
- Navabi use of buried initial statement
- new attribute (* synthesis, combinational *)
- NEW JOURNAL - CALL FOR PAPERS
- New proposal for ROM definitions in functions and tasks
- New updated Verilog Synthesis draft, D1.6
- Next 1364.1 WG meeting: Aug 4 teleconference
- Next 1364.1 working group meeting
- Next 1364.1 working group meeting: REMINDER!!!!
- OVI/Accellera Membership Rights
- Paper on Verilog-2001 Enhancements
- PASSED (SystemVerilog) - ANSI-Style Parameter Port List BNF Correction
- Please vote yes - 1364.1 ballot
- pragma suggestions
- pragmas
- pragmas (map_to_mux, etc.)
- problem with item 25
- Proposal for ROM and RAM modeling Styles
- Proposed BNF Fix for Verilog-2001 Parameter Errata
- Proposed styles for Inferring ROMs in Verilog
- Question on ROM // Your opinion on reply
- recursive instantiations of modules
- recursive instantiations of modules - MORE
- reminder of the word "directives" used in the draft...
- Reminder: Verilog Synthesis Working Group meeting
- Review of LRM sections for tomorrow's tele-conference
- Review of Syntax section
- Revisions to 1064.1 Section 4, Semantics
- ROM definitions from within tasks and functions
- ROM RAM Update 12/07/01 + SYNP attributes
- Romr/Ram spec comments
- Section 4.1, Section 5.2.2.1 and Section 5 in general
- Section 5.3 Modeling level-sensitive storage devices
- section 5.6 ROM // Question
- Section 7.7.9.1 - Initial Blocks - Illegal??
- Semantics proposal
- Server down time
- signed types
- signed types & case statement expressions.
- SLR Balloting Feedback Request (fwd)
- SLR Invitation to ballot on P260.1-SCC14 (fwd)
- Some review comments
- Spammers
- Special Issue of JASS Journal
- Std P1364-Y2K : 3.9 Integers not regarded as hardware registers???
- Std P1364-Y2K :3.10 Arrays // Examples correct???
- Stuff
- Submission deadline extension for the Special Sessions on Modern Digital System Synthesis at SCI'2001]
- Suggestions for synthesis tools
- Support for values x and z
- Synopsys support for Verilog-2001
- Synplicity Pragmas for IEEE VLOG Synthesis standard
- Synplify attributes.
- synthesis attribute question
- Synthesis-related papers available for down-load
- Test message: please delete
- the deadline for EUROMICRO'99 DSD Workshop is approaching
- The reflector is operational
- Tri-state push thru
- Updated 1364.1 v2.1 draft available
- Using initialization statements for defining initial setup of registers
- V2K1 configs and lib map
- vector bit-select in sensitivity list
- Verilog 1364 Proposal to replace meta-comment pragmas
- verilog 2000 feature list
- Verilog Black-Box Sample Model // + EDIF
- Verilog RTL Synthesis ballot passes!
- Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002
- Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES
- Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02
- Verilog RTL Synthesis standard: complimentary copy
- Verilog RTL Synthesis, Semantics Section 4.
- Verilog RTL Synthesis: It is a standard! It is a standard! An IEEE Standard!
- Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
- Verilog Synthesis draft 2.0
- Verilog Synthesis draft 2.0 // Comments
- Verilog Synthesis draft 2.0 // Comments // Krishna RSVP
- Verilog Synthesis Interoperability WG: NO MEETING ON MARCH 22
- Verilog Synthesis Interoperability Working Group
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Aug 10, '01
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Sep 07, '01
- Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01
- Verilog Synthesis Interoperability Working Group: Agendafor July 6, '01
- Verilog Synthesis subset spec
- Verilog Synthesis WG Meeting minutes: March 11, 2002
- Verilog Synthesis Working Group meeting: face to face
- Verilog2K synthesis features
- Verilog: ROMRAM Revision 2
- vlog 2000 feature list
- Working Group Chair Message CALL FOR NOMINATIONS: Han Karlsson Award
- Last message date: Wed Apr 06 2005 - 08:25:52 PDT
- Archived on: Wed Apr 06 2005 - 08:26:39 PDT