Subject: Re: Proposed styles for Inferring ROMs in Verilog
From: VhdlCohen@aol.com
Date: Wed Jul 11 2001 - 15:14:48 PDT
In a message dated 7/11/01 10:37:45 AM Pacific Daylight Time,
jbhasker@cadence.com writes:
<< 1. If "block_rom" was specified, where/how is the rom data to be stored
after
synthesis?>>
I would presume that this is tool specific. For FPGA, EDIF format is
probably the statndard. For ASIC, this might be the internal data base
format.
<<2. In the case stmt style, I guess you would restrict the case stmt to the
form
you have shown, i.e. there would be no other statements within the case
stmt
other than the assignments to rom data
and only the rom address would be the case expression? I guess we could
allow other statements within the always but the ROM address must be
present
in the always event list.>>
Correct. Might be better to only have code for the ROM only.
<<3. In the initial stmt style, again I guess the initial statement would be
restricted to have all rom assignments in one initial stmt (can you have
rom initializations in more than one initial statement?)>>
One initial statement only! Keep it simple.
<<4. The initial stmt and readmem styles: are they supported by any
vendors?>>
I thought that one vendor did, according to the newsgroup. I see no reason
why it should not or could not be supported.
<< 5. The cases you have described only handle asynchronous single port ROM.
How do you propose we handle synchronous ROMs?
>>
What is a "synchronous ROM"? I thought ROMs were like lookup tables, and
asynchronous by nature.
----------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/>
vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
--------------------------------------------------------------------------
------------------------------------------
This archive was generated by hypermail 2b28 : Wed Jul 11 2001 - 15:32:50 PDT