Subject: Re: Proposed styles for Inferring ROMs in Verilog
From: VhdlCohen@aol.com
Date: Wed Jul 11 2001 - 19:16:38 PDT
In a message dated 7/11/01 3:42:37 PM Pacific Daylight Time,
VhdlCohen@aol.com writes:
> <<4. The initial stmt and readmem styles: are they supported by any
> vendors?>>
> I thought that one vendor did, according to the newsgroup. I see no reason
> why it should not or could not be supported.
>
>
Altera provides tools to instantiate RAMs and ROMs, and to initialize ROMS
from files/ This is not within the HDL, but through a proprietary mechanism.
The point though is that the concept IS possible, and there really is no
reason as to why the initialization cannot be done via the $readmemh or
%readmemb as this would also facilitate simulation at the RTL level and use a
common RTL code for simulation and verification.
From Altera SUPPORT:
<A HREF="http://www.altera.com/support/software/eda_maxplus2/synopsys/fpgaex/fpxramv.htm">http://www.altera.com/support/software/eda_maxplus2/synopsys/fpgaex/fpxramv.ht
m
</A>
Instantiating RAM & ROM Functions in Verilog HDL
To instantiate other RAM and ROM functions in Verilog HDL, follow these steps:
Use the genmem utility to generate a memory model by typing the following
command at a DOS or UNIX prompt: genmem <memory type> <memory size> -verilog >
For example: genmem scfifo 16x8 -verilog >
Create a Verilog HDL design that instantiates the <memory name>.v function.
The genmem utility produces files with descriptive names that typically
include both the memory type and the memory size (e.g., scfifo_16x8_d.v).>
In MAX+PLUS II version 8.3 and lower, running genmem on a PC always creates
files named as genmem.vhd, genmem.cmp, and genmem.v, regardless of the memory
type and memory size values you specify.
(Optional for RAM functions) Specify an initial memory content file:
For ROM functions, you must specify the filename of an initial memory content
file in the Intel hexadecimal format (.hex) or the AlteraŽ Memory
Initialization File (.mif) format in the Parameter Statement, using the
LPM_FILE parameter. The filename must be the same as the instance name; e.g.,
the u1 instance name must be unique throughout the whole project, and must
contain only valid Verilog HDL name characters. The initialization file must
reside in the directory containing the project's design files.
For RAM functions, specifying a memory initialization file is optional. If
you want to use it, you must specify it in the Parameter Statement as
described above.>
The MIF format is supported only for specifying initial memory content when
compiling designs within MAX+PLUS II software. You cannot use an MIF to
perform simulation with Synopsys tools prior to MAX+PLUS II compilation.
If you use an Intel hexadecimal format file and wish to simulate the file
with the VHDL System Simulator Software (VSS) after MAX+PLUS II compilation,
you should use the Synopsys intelhex utility to translate the Intel
hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to
the Synopsys VHDL System Simulator Software Tool manual for details about
using the intelhex utility.
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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