Subject: Re: Proposed styles for Inferring ROMs in Verilog
From: VhdlCohen@aol.com
Date: Wed Jul 11 2001 - 19:26:17 PDT
In a message dated 7/11/01 3:42:37 PM Pacific Daylight Time,
VhdlCohen@aol.com writes:
> <<4. The initial stmt and readmem styles: are they supported by any
> vendors?>>
> I thought that one vendor did, according to the newsgroup. I see no reason
> why it should not or could not be supported.
>
>
More from Altera with file initialization. Not the use of proprietary LPM
ROM.
Create a Verilog HDL design that instantiates the <memory name> function.
Figure 1 shows a Verilog HDL design that instantiates asyn_rom_256x15.v, a
256 x 15 ROM function.Figure 1. Verilog HDL File with ROM Instantiation
(tstrom.v)
module tstrom (addr, enab, q);
parameter LPM_FILE = "u1.hex";
input [7:0] addr;
input enab;
output [14:0] q;
asyn_rom_256x15 // synopsys translate_off
#(LPM_FILE)
// synopsys translate_on
u1 (.Address(addr), .Q(q), .MemEnab(enab));
endmodule
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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