Subject: Re: Con Call MInutes, July 6, 2001
From: Michael McNamara (mac@verisity.com)
Date: Wed Jul 11 2001 - 02:43:35 PDT
Shalom Bresticker (r50386) writes:
> [1 <text/plain; us-ascii (7bit)>]
> Comments:
>
> * "There is some discussion about the attribute format, rtl_synthesis_full_case, or rtl_synthesis_full_case = true, or
> rtl_synthesis_full_case = 1"
>
> I think 1364-2001 is pretty clear.
> "rtl_synthesis_full_case" and "rtl_synthesis_full_case=1" are the same.
> No need for the "=true" version because you have these two versions.
> Today also, you just write "full_case".
>
> * "PraveenTiwari (Bhasker reported): More discussion is required
> regarding whether the LHS of an assignment should permit +:
> index ranges with a variable range per Praveen's email. Vector
> part select in both first and second ranges?"
>
> I'm not sure I understand this issue. What is "first range"
> and "second range"? 1364-2001 is clear that the "width_expr
> shall be a constant expression".
The intention of the committee was that one could use :+ on both the
left hand and right hand side of an assigment:
parameter width = 8, depth = 32; // Defaults
localparam size = depth * width;
...
i = 0;
while (i < size ) begin
bus[i:+ width ] = data[i:+ width ];
i = i + width;
end
Further, as Shalom states, the expression after the :+ must be a
constant expression.
>
> --
> **************************************************************************
> Shalom Bresticker Shalom.Bresticker@motorola.com
> Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
> P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
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