Subject: Re: Proposed styles for Inferring ROMs in Verilog
From: VhdlCohen@aol.com
Date: Thu Jul 12 2001 - 11:12:32 PDT
In a message dated 7/12/01 9:49:54 AM Pacific Daylight Time,
jbhasker@cadence.com writes:
> >> > What is a "synchronous ROM"? I thought ROMs were like lookup tables,
> and asynchronous by nature. >>>
>
> <Synchronous ROM only provide data at a specific clock edge. A Lucent
> standard
> cell library catalogue that I have has such blocks.>
Isn't that just an asynchronous ROM forllowed by a register? I see two
styles:
1. Register is AFTER the inferred ROM. Example:
module rom_case(z, a, clk);
output [3:0] z; // 4 wide
input [2:0] a; // address. 8 deep memory
input clk;
// proposed syntax
reg [3:0] romtemp /* syn_romstyle = block_rom */;
reg [3:0] z; // output
// Other potentials
// /* syn_romstyle = 1 */
// NOTE: To infer combinational logic instead of ROM, use
// /* syn_romstyle = logic */
always @(a) begin
case (a)
3'b000: romtemp = 4'b1011;
3'b001: romtemp = 4'b0001;
3'b100: romtemp = 4'b0011;
3'b110: romtemp = 4'b0010;
3'b111: romtemp = 4'b1110;
default: romtemp = 4'b0000;
endcase
end
always @(posedge clk)
z <= romtemp;
endmodule // rom_case
Other style is to put put the rom inside the clocked block. Example:
module romsync2(z, a, clk);
output [3:0] z; // 4 wide
input [2:0] a; // address. 8 deep memory
input clk;
// proposed syntax
reg [3:0] z; // output
// Other potentials
// /* syn_romstyle = 1 */
// NOTE: To infer combinational logic instead of ROM, use
// /* syn_romstyle = logic */
always @(posedge clk) begin
case (a)
3'b000: z = 4'b1011;
3'b001: z = 4'b0001;
3'b100: z = 4'b0011;
3'b110: z = 4'b0010;
3'b111: z = 4'b1110;
default: z = 4'b0000;
endcase
end
endmodule // romsync2
Both models synthesized OK with Synplify. It seems to me that the register
should be in a separate clocked process (1st example). That way, we could
standardize on other styles of ROM models, such as those with the "initial"
statements. >
>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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