/bbs/pub/vlog-synth By Thread
- Verilog Synthesis subset spec David Bishop (Fri May 29 1998 - 11:41:15 PDT)
- Test message: please delete Jayaram_Bhasker (Fri May 29 1998 - 12:39:06 PDT)
- The reflector is operational Jayaram_Bhasker (Fri May 29 1998 - 12:56:08 PDT)
- Editor Jayaram_Bhasker (Fri May 29 1998 - 13:08:15 PDT)
- Fwd: Re: Editor Yatin Trivedi (Tue Jun 02 1998 - 15:38:08 PDT)
- Reminder: Verilog Synthesis Working Group meeting Jayaram_Bhasker (Thu Jun 04 1998 - 06:24:52 PDT)
- Re: Critical need for HW design engineers Paul J. Menchini (Fri Jun 12 1998 - 12:31:08 PDT)
- Server down time David Bishop (Thu Jun 25 1998 - 06:31:24 PDT)
- Re: Stuff Steven Schulz (Thu Jun 25 1998 - 06:49:24 PDT)
- Edge-sensitive sequential logic Tommy Kelly (Fri Jun 26 1998 - 04:03:21 PDT)
- e-mail address David Bishop (Mon Jun 29 1998 - 05:33:24 PDT)
- Re: Working Group Chair Message CALL FOR NOMINATIONS: Han Karlsson Award jbhasker@lucent.com (Thu Jul 02 1998 - 11:49:15 PDT)
- IEEE approves PAR for Verilog Synthesis subset jbhasker@lucent.com (Thu Jul 02 1998 - 13:59:00 PDT)
- pragmas Michael McNamara (Sun Jul 05 1998 - 12:56:44 PDT)
- Meetings schedule, 1364.1 jbhasker@lucent.com (Mon Jul 06 1998 - 11:59:36 PDT)
- pragmas Michael McNamara (Mon Jul 06 1998 - 16:04:58 PDT)
- DATE'99 Call for papers villar@teisa.unican.es (Tue Jul 14 1998 - 02:36:07 PDT)
- FDL'98 Invitation Alain Vachoux (Wed Jul 15 1998 - 05:41:57 PDT)
- Spammers David Bishop (Thu Jul 16 1998 - 12:43:43 PDT)
- 1364.1 working group policy David Bishop (Thu Jul 16 1998 - 14:00:49 PDT)
- Next 1364.1 WG meeting: Aug 4 teleconference jbhasker@lucent.com (Thu Jul 16 1998 - 14:03:46 PDT)
- Revisions to 1064.1 Section 4, Semantics kcoffman@sos.net (Wed Jul 29 1998 - 07:11:48 PDT)
- Agenda for tomorrow tele-conference jbhasker@lucent.com (Mon Aug 03 1998 - 10:32:23 PDT)
- BNR draft items Don Hejna (Mon Aug 03 1998 - 18:31:57 PDT)
- Semantics proposal Shalom Bresticker (Tue Aug 04 1998 - 04:35:58 PDT)
- Re: pragmas (map_to_mux, etc.) Stefen Boyd (Wed Aug 05 1998 - 09:28:28 PDT)
- Minutes, Teleconference, Aug 4, 1998 kcoffman@sos.net (Sun Aug 09 1998 - 08:35:42 PDT)
- Verilog RTL Synthesis, Semantics Section 4. Ken Coffman (Mon Sep 07 1998 - 17:39:52 PDT)
- 1364.1 Semantics Section 4. Ken Coffman (Wed Oct 07 1998 - 06:46:33 PDT)
- EUROMICRO'99 DSD Workshop, Call for Papers lech@ics.ele.tue.nl (Thu Oct 08 1998 - 09:31:21 PDT)
- Re: function semantics jbhasker@lucent.com (Wed Nov 25 1998 - 05:42:25 PST)
- EUROMICRO'99 DSD Workshop, Call for Papers lech@ics.ele.tue.nl (Thu Dec 03 1998 - 02:36:38 PST)
- EUROMICRO'99 DSD Workshop lech@ics.ele.tue.nl (Tue Dec 15 1998 - 23:57:37 PST)
- FDL'99 Call for Contributions lech@ics.ele.tue.nl (Wed Dec 16 1998 - 05:47:28 PST)
- Back online jbhasker@lucent.com (Wed Jan 06 1999 - 07:55:39 PST)
- the deadline for EUROMICRO'99 DSD Workshop is approaching lech@ics.ele.tue.nl (Mon Feb 01 1999 - 05:38:10 PST)
- FDL conference lech@ics.ele.tue.nl (Mon Feb 01 1999 - 08:13:05 PST)
- 1364.1 Verilog Synthesis Working Group Meeting Jayaram Bhasker (Wed Feb 10 1999 - 09:09:02 PST)
- EUROMICRO'99: DSD Workshop - Last Call for Papers lech@ics.ele.tue.nl (Wed Feb 17 1999 - 07:24:12 PST)
- Call for Papers IEEE/DATC EDP '99 David Bishop (Wed Feb 17 1999 - 07:44:19 PST)
- Re: 1364.1 Verilog Synthesis Working Group Meeting: REMINDER Jayaram Bhasker (Fri Feb 19 1999 - 13:25:30 PST)
- Section 5.3 Modeling level-sensitive storage devices Shalom Bresticker (Mon Feb 22 1999 - 01:27:34 PST)
- Re: Section 4.1, Section 5.2.2.1 and Section 5 in general Alain RAYNAUD (Tue Feb 23 1999 - 01:08:29 PST)
- Verilog 1364 Proposal to replace meta-comment pragmas Tom Fitzpatrick (Tue Feb 23 1999 - 07:11:42 PST)
- Meeting Minutes: 1364.1 Verilog Synthesis Working Group Meeting Jayaram Bhasker (Wed Feb 24 1999 - 13:00:54 PST)
- `celldefine issue: Verilog RTL synthesis subset Jayaram Bhasker (Fri Feb 26 1999 - 06:17:47 PST)
- Hierarchical names: Verilog RTL synthesis Jayaram Bhasker (Fri Feb 26 1999 - 06:24:16 PST)
- Support for values x and z Jayaram Bhasker (Mon Mar 08 1999 - 13:12:11 PST)
- Review of Syntax section Jayaram Bhasker (Thu Mar 11 1999 - 11:28:02 PST)
- Re: Call for DASC WG Nominations Jayaram Bhasker (Fri Mar 12 1999 - 13:16:02 PST)
- Verilog Synthesis Working Group meeting: face to face Jayaram Bhasker (Thu Mar 25 1999 - 11:22:43 PST)
- draft 1.3 Shalom Bresticker (Mon Mar 29 1999 - 05:21:34 PST)
- DASC member Jayaram Bhasker (Wed Mar 31 1999 - 13:08:47 PST)
- NEW JOURNAL - CALL FOR PAPERS Nikitas Assimakopoulos (Thu Apr 01 1999 - 09:40:13 PST)
- Re: Modelling of level sensitive devices Apurva Kalia (Thu Apr 15 1999 - 21:30:13 PDT)
- Meeting Minutes: P1364.1 Verilog Synthesis WG Jayaram Bhasker (Fri Apr 23 1999 - 13:56:26 PDT)
- Compilation pragmas Jayaram Bhasker (Fri Apr 23 1999 - 14:12:08 PDT)
- full_case, parallel_case Jayaram Bhasker (Fri Apr 23 1999 - 14:28:37 PDT)
- Draft 1.4 Verilog RTL synthesis Jayaram Bhasker (Tue Apr 27 1999 - 12:42:56 PDT)
- Next 1364.1 working group meeting Jayaram Bhasker (Tue Apr 27 1999 - 12:47:49 PDT)
- Re: Next 1364.1 working group meeting: REMINDER!!!! Jayaram Bhasker (Thu May 06 1999 - 11:48:28 PDT)
- Functional Mismatches Clifford E. Cummings (Fri May 07 1999 - 09:00:26 PDT)
- (no subject) Cliff Cummings (Fri May 07 1999 - 14:30:36 PDT)
- Mismatch Paper PDF File - 2nd try Cliff Cummings (Fri May 07 1999 - 14:31:00 PDT)
- BTF Conference Call - Verilog Attributes & Pragmas Discussion Clifford E. Cummings (Fri May 07 1999 - 14:41:10 PDT)
- IEEE Fees?? Clifford E. Cummings (Mon May 10 1999 - 08:30:25 PDT)
- DASC & SA Fees? Clifford E. Cummings (Mon May 10 1999 - 13:41:48 PDT)
- Functional Mismatches Paper on the vlog-synth Web Site Clifford E. Cummings (Tue May 18 1999 - 17:25:16 PDT)
- Comments on 1364.1 D1.4 Ken Coffman (Tue May 25 1999 - 07:12:44 PDT)
- Re: ! vs. ~ Shalom Bresticker (Thu May 27 1999 - 03:44:25 PDT)
- JASS Journal - Call for Papers Nikitas Assimakopoulos (Wed Jun 16 1999 - 06:40:40 PDT)
- Special Issue of JASS Journal Nikitas Assimakopoulos (Tue Sep 14 1999 - 00:48:48 PDT)
- DSD2000 Symposium, First Call for Papers nunez@cma.ulpgc.es (Wed Oct 20 1999 - 04:06:36 PDT)
- DDECS 2000 Call For Papers lech@ics.ele.tue.nl (Mon Dec 06 1999 - 02:45:07 PST)
- International HDL Conference 2000 CALL FOR PAPERS Jayaram Bhasker (Fri Dec 10 1999 - 11:22:45 PST)
- [Fwd: JOURNAL OF SYSTEMS ARCHITECTURE, Final Call For Papers] David Bishop (Tue Feb 08 2000 - 10:13:34 PST)
- OVI/Accellera Membership Rights Jayaram Bhasker (Thu Jun 01 2000 - 05:01:33 PDT)
- [Fwd: Final Call for Papers, NOTE 9/22/00 deadline extension] David Bishop (Fri Sep 15 2000 - 10:57:29 PDT)
- Here we go again ... Jayaram Bhasker (Tue Sep 26 2000 - 06:18:16 PDT)
- verilog 2000 feature list Jayaram Bhasker (Wed Sep 27 2000 - 06:32:54 PDT)
- problem with item 25 Stefen Boyd (Wed Sep 27 2000 - 12:27:50 PDT)
- FWD: RE: verilog 2000 feature list David Bishop (Wed Sep 27 2000 - 17:07:48 PDT)
- Re: SLR Balloting Feedback Request (fwd) Jayaram Bhasker (Mon Oct 16 2000 - 11:26:19 PDT)
- Std P1364-Y2K :3.10 Arrays // Examples correct??? VhdlCohen@aol.com (Thu Oct 26 2000 - 16:32:48 PDT)
- Std P1364-Y2K : 3.9 Integers not regarded as hardware registers??? VhdlCohen@aol.com (Thu Oct 26 2000 - 16:32:39 PDT)
- Submission deadline extension for the Special Sessions on Modern Digital System Synthesis at SCI'2001] David Bishop (Wed Feb 07 2001 - 07:50:52 PST)
- LRM 5.x: Unclear about when block refires on same event that changed VhdlCohen@aol.com (Tue Feb 13 2001 - 10:39:51 PST)
- Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01 J. Bhasker (Wed May 30 2001 - 06:09:43 PDT)
- Verilog2K synthesis features J. Bhasker (Fri Jun 01 2001 - 11:12:47 PDT)
- New updated Verilog Synthesis draft, D1.6 J. Bhasker (Fri Jun 15 2001 - 08:41:23 PDT)
- Verilog2K synthesis features J. Bhasker (Fri Jun 15 2001 - 08:54:38 PDT)
- Inferring ROMs in Verilog VhdlCohen@aol.com (Fri Jun 22 2001 - 09:24:23 PDT)
- Re: Inferring RAMs in Verilog VhdlCohen@aol.com (Sat Jun 23 2001 - 12:06:17 PDT)
- 5.4 Modeling three-state drivers VhdlCohen@aol.com (Fri Jun 29 2001 - 11:53:28 PDT)
- Using initialization statements for defining initial setup of registers VhdlCohen@aol.com (Tue Jul 03 2001 - 13:38:37 PDT)
- Re: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01 Jayaram Bhasker (Thu Jul 05 2001 - 09:01:02 PDT)
- Paper on Verilog-2001 Enhancements Clifford E. Cummings (Fri Jul 06 2001 - 12:10:09 PDT)
- vlog 2000 feature list Jayaram Bhasker (Fri Jul 06 2001 - 12:57:21 PDT)
- Proposed styles for Inferring ROMs in Verilog VhdlCohen@aol.com (Fri Jul 06 2001 - 19:05:11 PDT)
- FDL 2001 Advance Program Announcement Jayaram Bhasker (Wed Jul 11 2001 - 07:57:51 PDT)
- attributes Joseph P. Wetstein (Wed Jul 11 2001 - 10:12:37 PDT)
- fullcase/parallel case (fwd) Jayaram Bhasker (Wed Jul 11 2001 - 10:13:38 PDT)
- Draft Proposal: 5.6 Modeling Read-Only Memories (ROM); 5.7 RAM VhdlCohen@aol.com (Mon Jul 16 2001 - 11:33:19 PDT)
- HDLCon 2002 Call for Papers Jayaram Bhasker (Thu Jul 19 2001 - 08:41:24 PDT)
- constant function Gilbert Nguyen (Thu Jul 19 2001 - 09:52:56 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Aug 10, '01 Jayaram Bhasker (Mon Aug 06 2001 - 08:49:31 PDT)
- Re: Assigning / testing different sizes -- shouldn't we restrict the use? VhdlCohen@aol.com (Mon Aug 06 2001 - 14:40:00 PDT)
- Generate & defparams in Vlog-2001. Krishna Garlapati (Tue Aug 07 2001 - 16:10:04 PDT)
- Review of LRM sections for tomorrow's tele-conference Sashi Obilisetty (Thu Aug 09 2001 - 15:06:59 PDT)
- RE: Verilog Synthesis Interoperability Working Group Gilbert Nguyen (Fri Aug 10 2001 - 10:56:21 PDT)
- Proposal for ROM and RAM modeling Styles VhdlCohen@aol.com (Fri Aug 10 2001 - 11:43:37 PDT)
- Fwd: Proposal for ROM and RAM modeling Styles VhdlCohen@aol.com (Sun Aug 12 2001 - 20:49:15 PDT)
- case-generate grammar issues. Krishna Garlapati (Wed Aug 22 2001 - 17:06:24 PDT)
- V2K1 configs and lib map Stefen Boyd (Wed Aug 29 2001 - 17:04:40 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Sep 07, '01 Jayaram Bhasker (Thu Aug 30 2001 - 10:27:08 PDT)
- Navabi use of buried initial statement Ken Coffman (Sat Sep 01 2001 - 10:58:27 PDT)
- Synthesis-related papers available for down-load Clifford E. Cummings (Fri Sep 07 2001 - 11:01:15 PDT)
- Conference Call Minutes, Aug 10, 2001 Jayaram Bhasker (Mon Sep 10 2001 - 12:40:46 PDT)
- Romr/Ram spec comments VhdlCohen@aol.com (Thu Sep 13 2001 - 12:57:44 PDT)
- Meeting minutes - Verilog Synthesis Working Group Meeting: Sept 7, 2001 Jayaram Bhasker (Fri Sep 14 2001 - 07:20:02 PDT)
- Synopsys support for Verilog-2001 Shalom Bresticker (Sun Sep 23 2001 - 02:01:47 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01 J. Bhasker (Mon Oct 01 2001 - 08:41:34 PDT)
- [Fwd: Some comments on IEEE P1364.1/D1.7] David Bishop (Thu Oct 04 2001 - 19:20:06 PDT)
- FW: J. Bhasker (Fri Oct 05 2001 - 07:04:01 PDT)
- Verilog: ROMRAM Revision 2 VhdlCohen@aol.com (Fri Oct 05 2001 - 15:45:59 PDT)
- Initial Blocks fail with Synopsys Tools Clifford E. Cummings (Fri Oct 05 2001 - 17:40:26 PDT)
- For page 64, Section 4, example 4.4.3 -- value can't be verified tiao@agere.com (Mon Oct 08 2001 - 12:53:45 PDT)
- example may be improved... tiao@agere.com (Mon Oct 08 2001 - 12:57:53 PDT)
- [Fwd: Exemplar Handling of Initial Statement] David Bishop (Tue Oct 09 2001 - 13:38:16 PDT)
- signed types & case statement expressions. Krishna Garlapati (Tue Oct 09 2001 - 15:41:06 PDT)
- correction in my earlier email. Krishna Garlapati (Tue Oct 09 2001 - 15:50:32 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01 J. Bhasker (Tue Oct 23 2001 - 11:50:56 PDT)
- Re: Attributes and constant expressions Stefen Boyd (Wed Oct 24 2001 - 14:03:46 PDT)
- D1_7 Pragmas Proposal - Section 6 - 20011025 Clifford E. Cummings (Thu Oct 25 2001 - 17:17:21 PDT)
- Minor corrections to IEEE P1364.1 / D1.7 VhdlCohen@aol.com (Thu Nov 01 2001 - 10:25:24 PST)
- ROM definitions from within tasks and functions VhdlCohen@aol.com (Thu Nov 01 2001 - 12:19:54 PST)
- New proposal for ROM definitions in functions and tasks VhdlCohen@aol.com (Fri Nov 02 2001 - 13:37:44 PST)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01 J. Bhasker (Mon Dec 03 2001 - 10:54:50 PST)
- D1_7 Pragmas Proposal - Section 6 - (updated 20011206) Clifford E. Cummings (Thu Dec 06 2001 - 07:17:32 PST)
- Cadence (Ambit) pragmas Paul Graham (Fri Dec 07 2001 - 09:08:12 PST)
- ROM RAM Update 12/07/01 + SYNP attributes VhdlCohen@aol.com (Fri Dec 07 2001 - 16:21:35 PST)
- pragma suggestions Muzaffer Kal (Sun Dec 09 2001 - 00:58:42 PST)
- Synplicity Pragmas for IEEE VLOG Synthesis standard VhdlCohen@aol.com (Mon Dec 10 2001 - 17:41:48 PST)
- VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper: VhdlCohen@aol.com (Tue Dec 11 2001 - 21:23:08 PST)
- Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper VhdlCohen@aol.com (Wed Dec 12 2001 - 06:26:58 PST)
- FYI: Initialization of RAM VhdlCohen@aol.com (Wed Dec 12 2001 - 10:54:32 PST)
- Fwd: Implicit FSMs style with mutiple clocks VhdlCohen@aol.com (Wed Dec 12 2001 - 13:45:33 PST)
- RE: FSM Enhancement Goals and Thoughts Clifford E. Cummings (Wed Dec 12 2001 - 16:17:16 PST)
- Re: FSM Enhancement Goals and Thoughts Clifford E. Cummings (Thu Dec 13 2001 - 09:43:14 PST)
- Re: Implicit FSMs style with mutiple clocks VhdlCohen@aol.com (Fri Dec 14 2001 - 23:31:11 PST)
- new attribute (* synthesis, combinational *) Stefen Boyd (Mon Dec 17 2001 - 11:46:29 PST)
- pragmas Shalom Bresticker (Tue Dec 18 2001 - 02:42:07 PST)
- FW: 1364.1 draft 1.8 J. Bhasker (Thu Jan 03 2002 - 11:02:29 PST)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02 J. Bhasker (Tue Jan 08 2002 - 06:19:28 PST)
- Synplify attributes. Krishna Garlapati (Thu Jan 10 2002 - 18:29:16 PST)
- Re: Asynchronous design VhdlCohen@aol.com (Fri Jan 11 2002 - 10:40:22 PST)
- reminder of the word "directives" used in the draft... Jenjen_Tiao (Fri Jan 11 2002 - 10:58:58 PST)
- Verilog Black-Box Sample Model // + EDIF VhdlCohen@aol.com (Sun Jan 13 2002 - 15:30:37 PST)
- Blackbox attribute VhdlCohen@aol.com (Wed Jan 16 2002 - 11:34:16 PST)
- Attribute "encoding" Jayaram Bhasker (Tue Jan 22 2002 - 14:04:19 PST)
- Draft 1.9 // synthesis encoding vs state_machine VhdlCohen@aol.com (Wed Jan 30 2002 - 15:45:11 PST)
- (* synthesis, keep [=<optional_value>] *) VhdlCohen@aol.com (Wed Jan 30 2002 - 15:45:14 PST)
- Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002 Jayaram Bhasker (Mon Feb 04 2002 - 11:13:19 PST)
- Re: (* synthesis, keep [=<optional_value>] *) // ALL? VhdlCohen@aol.com (Fri Feb 08 2002 - 08:46:52 PST)
- RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES Jayaram Bhasker (Fri Feb 08 2002 - 11:57:19 PST)
- FW: Invitation to Ballot for P1364.1 Jayaram Bhasker (Tue Feb 12 2002 - 08:24:12 PST)
- FW: Verilog Synthesis draft 2.0 Jayaram Bhasker (Wed Feb 13 2002 - 06:16:14 PST)
- Verilog Synthesis draft 2.0 // Comments VhdlCohen@aol.com (Sun Feb 17 2002 - 13:35:57 PST)
- Re: Verilog Synthesis draft 2.0 // Comments // Krishna RSVP VhdlCohen@aol.com (Mon Feb 25 2002 - 10:31:28 PST)
- FW: Editorial coordination on draft 1364.1 Jayaram Bhasker (Tue Feb 26 2002 - 09:54:24 PST)
- Some review comments Jayaram Bhasker (Thu Feb 28 2002 - 12:07:27 PST)
- Annex B Replacement Proposal Clifford E. Cummings (Fri Mar 01 2002 - 11:53:03 PST)
- 1364.1 WG meeting at HDLCON Jayaram Bhasker (Wed Mar 06 2002 - 07:20:47 PST)
- Keep Attribute // An update VhdlCohen@aol.com (Wed Mar 06 2002 - 09:27:17 PST)
- 1364.1 WG meeting at HDLCON Jayaram Bhasker (Wed Mar 06 2002 - 11:24:21 PST)
- recursive instantiations of modules VhdlCohen@aol.com (Fri Mar 08 2002 - 14:42:53 PST)
- Re: recursive instantiations of modules - MORE M Ciletti (Sun Mar 10 2002 - 14:38:54 PST)
- Verilog Synthesis WG Meeting minutes: March 11, 2002 Jayaram Bhasker (Fri Mar 15 2002 - 13:47:24 PST)
- Re: Assignments in the Verilog RTL Synthesizes draft Clifford E. Cummings (Sun Mar 17 2002 - 07:56:51 PST)
- Verilog Synthesis Interoperability WG: NO MEETING ON MARCH 22 Jayaram Bhasker (Mon Mar 18 2002 - 12:52:10 PST)
- Tri-state push thru VhdlCohen@aol.com (Tue Mar 19 2002 - 08:59:57 PST)
- RE: Assignments in the Verilog RTL Synthesizes draft Jayaram Bhasker (Mon Mar 25 2002 - 14:22:17 PST)
- Another attribute: test_port Jayaram Bhasker (Wed Mar 27 2002 - 08:27:09 PST)
- assigning 'X' Muzaffer Kal (Thu Mar 28 2002 - 01:08:28 PST)
- correction to section 5.4 Muzaffer Kal (Thu Mar 28 2002 - 01:15:28 PST)
- Updated 1364.1 v2.1 draft available Jayaram Bhasker (Fri Mar 29 2002 - 07:47:59 PST)
- Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02 Jayaram Bhasker (Fri Mar 29 2002 - 07:53:58 PST)
- attribute: test_port // more comments VhdlCohen@aol.com (Fri Mar 29 2002 - 12:45:07 PST)
- 6.1 Synthesis attributes // minor syntax update VhdlCohen@aol.com (Fri Mar 29 2002 - 12:53:14 PST)
- 1364.1 v2.1 draft COMMENTS VhdlCohen@aol.com (Fri Mar 29 2002 - 14:52:51 PST)
- section 5.6 ROM // Question VhdlCohen@aol.com (Fri Apr 05 2002 - 14:42:49 PST)
- Section 7.7.9.1 - Initial Blocks - Illegal?? Clifford E. Cummings (Wed Apr 10 2002 - 16:02:43 PDT)
- Proposed BNF Fix for Verilog-2001 Parameter Errata Clifford E. Cummings (Thu Apr 11 2002 - 12:13:20 PDT)
- Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002 Clifford E. Cummings (Fri Apr 12 2002 - 09:40:55 PDT)
- Floating point synthesis, call for participation David Bishop (Fri Apr 12 2002 - 19:53:37 PDT)
- PASSED (SystemVerilog) - ANSI-Style Parameter Port List BNF Correction Clifford E. Cummings (Mon Apr 15 2002 - 14:46:40 PDT)
- Draft D2.2 for ballot Jayaram Bhasker (Thu Apr 25 2002 - 13:27:24 PDT)
- 1364.1 in ballot Jayaram Bhasker (Wed May 15 2002 - 13:02:53 PDT)
- Please vote yes - 1364.1 ballot Clifford E. Cummings (Wed Jun 12 2002 - 14:36:21 PDT)
- Re: Looking for peace in the VHDL and Verilog Attributes John Michael Williams (Thu Jun 13 2002 - 13:35:24 PDT)
- Verilog RTL Synthesis ballot passes! Jbhasker7@aol.com (Wed Jun 26 2002 - 08:12:10 PDT)
- synthesis attribute question Muzaffer Kal (Sat Jul 06 2002 - 13:39:02 PDT)
- Question on ROM // Your opinion on reply VhdlCohen@aol.com (Sat Jul 13 2002 - 11:35:34 PDT)
- Ballot feedback: test_port Jbhasker7@aol.com (Mon Jul 15 2002 - 12:46:52 PDT)
- Ballot comment: multiplication Jbhasker7@aol.com (Mon Jul 15 2002 - 12:57:59 PDT)
- vector bit-select in sensitivity list Shalom Bresticker (Thu Aug 08 2002 - 03:06:16 PDT)
- Ballot response document Jayaram Bhasker (Mon Aug 19 2002 - 06:38:48 PDT)
- feedback for the ballot response document Jenjen Tiao (Wed Aug 21 2002 - 13:25:11 PDT)
- 1364.1 ballot responses Shalom.Bresticker@motorola.com (Mon Aug 26 2002 - 05:43:27 PDT)
- Making ballot responses consistent Jayaram Bhasker (Mon Aug 26 2002 - 06:46:40 PDT)
- 1364.1 pragmas Shalom Bresticker (Wed Aug 28 2002 - 01:02:40 PDT)
- 1364.1: ROM and RAM modeling Shalom Bresticker (Wed Aug 28 2002 - 01:12:48 PDT)
- 1364.1 comments Shalom Bresticker (Wed Aug 28 2002 - 06:23:56 PDT)
- [Fwd: BOUNCE vlog-synth@eda.org: Non-member submission from[Daryl.Stewart@tenisontech.com]] David Bishop (Wed Sep 04 2002 - 04:33:19 PDT)
- 1364.1 recirculation ballot Jayaram Bhasker (Wed Sep 11 2002 - 07:34:41 PDT)
- 1364.1 passes second recirculation ballot Jayaram Bhasker (Mon Sep 30 2002 - 06:10:25 PDT)
- Comments on P1364.1/Draft 2.3 Shalom Bresticker (Tue Oct 01 2002 - 00:48:15 PDT)
- 6.3.2 Shalom.Bresticker@motorola.com (Sun Oct 06 2002 - 02:32:01 PDT)
- Suggestions for synthesis tools VhdlCohen@aol.com (Fri Oct 18 2002 - 17:59:37 PDT)
- Attribute KEEP vs NO_DUPLICATE & "clock uncertainty". VhdlCohen@aol.com (Tue Oct 22 2002 - 07:31:27 PDT)
- Verilog RTL Synthesis: It is a standard! It is a standard! An IEEE Standard! Jayaram Bhasker (Mon Dec 16 2002 - 05:12:08 PST)
- Verilog RTL Synthesis standard: complimentary copy Jayaram Bhasker (Wed Dec 18 2002 - 12:14:32 PST)
- FW: SLR Invitation to ballot on P260.1-SCC14 (fwd) Jayaram Bhasker (Wed Jan 08 2003 - 12:50:47 PST)
- [vlog-synth] Call for Contributions FDL 2003 David Bishop (Thu Mar 13 2003 - 14:55:49 PST)
- [vlog-synth] FDL'03 David Bishop (Tue Mar 18 2003 - 11:45:38 PST)
- [vlog-synth] FW: Electronic Standards Delivery Issue Jayaram Bhasker (Tue Jun 10 2003 - 10:10:50 PDT)
- [vlog-synth] DVCon 2004 Call For Papers Jayaram Bhasker (Tue Jul 01 2003 - 07:55:57 PDT)
- [vlog-synth] FW: DASC: draft procedures on web site Jayaram Bhasker (Fri Nov 07 2003 - 08:19:43 PST)
- [vlog-synth] FW: Awards for standards activities Jayaram Bhasker (Tue Nov 25 2003 - 07:17:41 PST)
- [vlog-synth] Verilog 2005 Jayaram Bhasker (Tue Jan 13 2004 - 08:10:10 PST)
- [vlog-synth] [Fwd: Last Call for Papers - EDP 2004 - Design Process Workshop] David Bishop (Fri Feb 13 2004 - 18:00:17 PST)
- [vlog-synth] This is a test message - please ignore. Jayaram Bhasker (Mon Mar 08 2004 - 12:37:08 PST)
- [vlog-synth] Signed Multiplier generation Biswas, Shiladitya (Sun Mar 28 2004 - 23:22:05 PST)
- [vlog-synth] Hey, dude, it's me ^_^ :P dbishop@server.vhdl.org (Tue Mar 02 2004 - 10:06:41 PST)
- [vlog-synth] Dersigning FSM Biswas, Shiladitya (Thu May 27 2004 - 07:02:54 PDT)
- [vlog-synth] FW: IEEE Std 1076.6-2004 and IEEE Std 1364.1-2002 Jayaram Bhasker (Wed Apr 06 2005 - 08:25:44 PDT)
- Last message date: Wed Apr 06 2005 - 08:25:52 PDT
- Archived on: Wed Apr 06 2005 - 08:26:38 PDT