`celldefine issue: Verilog RTL synthesis subset

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Here are the various choices:

A. Ignore these directives - in which case, user may have to put a rtl_synthesis
on/off around the module that is enclosed by `celldefine.

B. Issue error - User may have to put rtl_synthesis on/off around `celldefine
\ `endcelldefine.

C. Interpret `celldefine\`endcelldefine as rtl_synthesis off/on respectively.

Please send in your feedback by Mar 6.

- bhasker

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