Since I brought this up, I personally think the best is to adapt
choice C. This will accomplish our intended task of ignoring the directives,
and in essence ignoring the whole context of what the directives describe.
This also accomplish the ease of use/adaptation for any existing models.
Users will not have to change anything and the intended task would have
been done at the same time. Thanks.
Jenjen
> From owner-vlog-synth@eda.org Fri Feb 26 09:22 EST 1999
> X-Authentication-Warning: server.eda.org: majordom set sender to owner-vlog-synth@eda.org using -f
> Date: Fri, 26 Feb 1999 09:17:47 -0500 (EST)
> From: Jayaram Bhasker <jbhasker>
> To: vlog-synth@eda.org
> Subject: `celldefine issue: Verilog RTL synthesis subset
> X-Sun-Charset: US-ASCII
> Sender: owner-vlog-synth@eda.org
> Content-Type: text
> Content-Length: 489
>
> One issue identified at the last telecon was how to support `celldefine \
> `endcelldefine.
>
> Here are the various choices:
>
> A. Ignore these directives - in which case, user may have to put a rtl_synthesis
> on/off around the module that is enclosed by `celldefine.
>
> B. Issue error - User may have to put rtl_synthesis on/off around `celldefine
> \ `endcelldefine.
>
> C. Interpret `celldefine\`endcelldefine as rtl_synthesis off/on respectively.
>
> Please send in your feedback by Mar 6.
>
> - bhasker
>
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