Hierarchical names for nets and registers should not be supported. Many
"experts" would consider them bad practice in RTL code. In any case, do
any current RTL synthesis tools support them? I think not.
On the other hand, it would be a step forward, in my opinion, to support
hierarchical names for parameters, tasks and functions, so that one
could use the Verilog module in the same way as a VHDL package, i.e. to
structure the global name space. This would allow a more structured way
of sharing common declarations than either of the two commonly used
alternatives: `define or `include.
-- John Aynsley DOULOS Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom Tel: +44 1425 471223 Email: john@doulos.com Fax: +44 1425 471573 Web: http://www.doulos.com