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Fri May 29 1998 - 11:45:51 PDT,
Ending
Wed Apr 06 2005 - 08:25:52 PDT
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Fri May 29 1998 - 11:41:15 PDT
Verilog Synthesis subset spec
David Bishop
Fri May 29 1998 - 12:39:06 PDT
Test message: please delete
Jayaram_Bhasker
Fri May 29 1998 - 12:56:08 PDT
The reflector is operational
Jayaram_Bhasker
Fri May 29 1998 - 13:08:15 PDT
Editor
Jayaram_Bhasker
Tue Jun 02 1998 - 15:38:08 PDT
Fwd: Re: Editor
Yatin Trivedi
Thu Jun 04 1998 - 06:24:52 PDT
Reminder: Verilog Synthesis Working Group meeting
Jayaram_Bhasker
Fri Jun 12 1998 - 12:31:08 PDT
Re: Critical need for HW design engineers
Paul J. Menchini
Thu Jun 25 1998 - 06:31:24 PDT
Server down time
David Bishop
Thu Jun 25 1998 - 06:49:24 PDT
Re: Stuff
Steven Schulz
Fri Jun 26 1998 - 04:03:21 PDT
Edge-sensitive sequential logic
Tommy Kelly
Mon Jun 29 1998 - 03:49:48 PDT
Re: Edge-sensitive sequential logic
Tommy Kelly
Mon Jun 29 1998 - 04:05:13 PDT
Re: Edge-sensitive sequential logic
Apurva Kalia
Mon Jun 29 1998 - 05:33:24 PDT
e-mail address
David Bishop
Thu Jul 02 1998 - 11:46:53 PDT
Re: Stuff
jbhasker@lucent.com
Thu Jul 02 1998 - 11:49:15 PDT
Re: Working Group Chair Message CALL FOR NOMINATIONS: Han Karlsson Award
jbhasker@lucent.com
Thu Jul 02 1998 - 13:59:00 PDT
IEEE approves PAR for Verilog Synthesis subset
jbhasker@lucent.com
Sun Jul 05 1998 - 12:56:44 PDT
pragmas
Michael McNamara
Mon Jul 06 1998 - 01:01:37 PDT
Re: pragmas
Alain RAYNAUD
Mon Jul 06 1998 - 06:51:49 PDT
Re: Edge-sensitive sequential logic
jbhasker@lucent.com
Mon Jul 06 1998 - 07:00:01 PDT
Re: Edge-sensitive sequential logic
jbhasker@lucent.com
Mon Jul 06 1998 - 07:01:23 PDT
Re: Edge-sensitive sequential logic
jbhasker@lucent.com
Mon Jul 06 1998 - 07:05:12 PDT
Re: Edge-sensitive sequential logic
jbhasker@lucent.com
Mon Jul 06 1998 - 10:20:52 PDT
Re: pragmas
jbhasker@lucent.com
Mon Jul 06 1998 - 10:30:16 PDT
Re: pragmas
jbhasker@lucent.com
Mon Jul 06 1998 - 10:59:49 PDT
Re: pragmas
Michael McNamara
Mon Jul 06 1998 - 11:15:16 PDT
Re: pragmas
jbhasker@lucent.com
Mon Jul 06 1998 - 11:59:36 PDT
Meetings schedule, 1364.1
jbhasker@lucent.com
Mon Jul 06 1998 - 12:08:49 PDT
Re: pragmas
Erich Marschner
Mon Jul 06 1998 - 12:09:49 PDT
Re: pragmas
Don Hejna
Mon Jul 06 1998 - 12:33:22 PDT
Re: pragmas
Ken Coffman
Mon Jul 06 1998 - 16:04:58 PDT
pragmas
Michael McNamara
Mon Jul 06 1998 - 17:22:47 PDT
Re: pragmas
frm145
Mon Jul 06 1998 - 19:59:23 PDT
Re: pragmas
Clifford E. Cummings
Tue Jul 07 1998 - 11:07:19 PDT
Re: pragmas
Don Hejna
Tue Jul 07 1998 - 22:42:58 PDT
Re: pragmas
Apurva Kalia
Tue Jul 14 1998 - 02:36:07 PDT
DATE'99 Call for papers
villar@teisa.unican.es
Wed Jul 15 1998 - 05:41:57 PDT
FDL'98 Invitation
Alain Vachoux
Thu Jul 16 1998 - 12:43:43 PDT
Spammers
David Bishop
Thu Jul 16 1998 - 14:00:49 PDT
1364.1 working group policy
David Bishop
Thu Jul 16 1998 - 14:03:46 PDT
Next 1364.1 WG meeting: Aug 4 teleconference
jbhasker@lucent.com
Tue Jul 21 1998 - 13:29:04 PDT
Re: Next 1364.1 WG meeting: Aug 4 teleconference
jbhasker@lucent.com
Wed Jul 29 1998 - 07:11:48 PDT
Revisions to 1064.1 Section 4, Semantics
kcoffman@sos.net
Wed Jul 29 1998 - 12:07:55 PDT
Re: Revisions to 1064.1 Section 4, Semantics
mcurry@ti.com
Wed Jul 29 1998 - 23:36:37 PDT
Re: Revisions to 1064.1 Section 4, Semantics
Shalom Bresticker
Mon Aug 03 1998 - 10:32:23 PDT
Agenda for tomorrow tele-conference
jbhasker@lucent.com
Mon Aug 03 1998 - 18:31:57 PDT
BNR draft items
Don Hejna
Tue Aug 04 1998 - 04:35:58 PDT
Semantics proposal
Shalom Bresticker
Wed Aug 05 1998 - 09:11:51 PDT
Re: pragmas
Stefen Boyd
Wed Aug 05 1998 - 09:28:28 PDT
Re: pragmas (map_to_mux, etc.)
Stefen Boyd
Sun Aug 09 1998 - 08:35:42 PDT
Minutes, Teleconference, Aug 4, 1998
kcoffman@sos.net
Mon Aug 10 1998 - 03:51:39 PDT
Re: Minutes, Teleconference, Aug 4, 1998
Shalom Bresticker
Tue Aug 11 1998 - 09:50:13 PDT
Re: Minutes, Teleconference, Aug 4, 1998
Ken Coffman
Mon Aug 24 1998 - 12:08:29 PDT
Re:BNR draft items
Don Hejna
Thu Aug 27 1998 - 08:34:43 PDT
Re:BNR draft items
jbhasker@lucent.com
Mon Sep 07 1998 - 17:39:52 PDT
Verilog RTL Synthesis, Semantics Section 4.
Ken Coffman
Wed Sep 09 1998 - 06:21:22 PDT
Re: Verilog RTL Synthesis, Semantics Section 4.
Ken Coffman
Wed Oct 07 1998 - 06:46:33 PDT
1364.1 Semantics Section 4.
Ken Coffman
Thu Oct 08 1998 - 09:31:21 PDT
EUROMICRO'99 DSD Workshop, Call for Papers
lech@ics.ele.tue.nl
Thu Oct 08 1998 - 11:45:10 PDT
Re: 1364.1 Semantics Section 4.
jbhasker@lucent.com
Wed Nov 25 1998 - 05:42:25 PST
Re: function semantics
jbhasker@lucent.com
Thu Dec 03 1998 - 02:36:38 PST
EUROMICRO'99 DSD Workshop, Call for Papers
lech@ics.ele.tue.nl
Tue Dec 15 1998 - 23:57:37 PST
EUROMICRO'99 DSD Workshop
lech@ics.ele.tue.nl
Wed Dec 16 1998 - 05:47:28 PST
FDL'99 Call for Contributions
lech@ics.ele.tue.nl
Wed Jan 06 1999 - 07:55:39 PST
Back online
jbhasker@lucent.com
Mon Feb 01 1999 - 05:38:10 PST
the deadline for EUROMICRO'99 DSD Workshop is approaching
lech@ics.ele.tue.nl
Mon Feb 01 1999 - 08:13:05 PST
FDL conference
lech@ics.ele.tue.nl
Wed Feb 10 1999 - 09:09:02 PST
1364.1 Verilog Synthesis Working Group Meeting
Jayaram Bhasker
Wed Feb 17 1999 - 07:24:12 PST
EUROMICRO'99: DSD Workshop - Last Call for Papers
lech@ics.ele.tue.nl
Wed Feb 17 1999 - 07:44:19 PST
Call for Papers IEEE/DATC EDP '99
David Bishop
Fri Feb 19 1999 - 13:25:30 PST
Re: 1364.1 Verilog Synthesis Working Group Meeting: REMINDER
Jayaram Bhasker
Mon Feb 22 1999 - 01:27:34 PST
Section 5.3 Modeling level-sensitive storage devices
Shalom Bresticker
Tue Feb 23 1999 - 01:08:29 PST
Re: Section 4.1, Section 5.2.2.1 and Section 5 in general
Alain RAYNAUD
Tue Feb 23 1999 - 07:11:42 PST
Verilog 1364 Proposal to replace meta-comment pragmas
Tom Fitzpatrick
Wed Feb 24 1999 - 13:00:54 PST
Meeting Minutes: 1364.1 Verilog Synthesis Working Group Meeting
Jayaram Bhasker
Wed Feb 24 1999 - 13:37:52 PST
Re: Section 5.3 Modeling level-sensitive storage devices
Jayaram Bhasker
Fri Feb 26 1999 - 06:17:47 PST
`celldefine issue: Verilog RTL synthesis subset
Jayaram Bhasker
Fri Feb 26 1999 - 06:24:16 PST
Hierarchical names: Verilog RTL synthesis
Jayaram Bhasker
Fri Feb 26 1999 - 06:31:19 PST
Re: Hierarchical names: Verilog RTL synthesis
Alain RAYNAUD
Fri Feb 26 1999 - 07:42:40 PST
Re: `celldefine issue: Verilog RTL synthesis subset
Jenjen Tiao
Wed Mar 03 1999 - 05:53:45 PST
Re: Hierarchical names: Verilog RTL synthesis
Apurva Kalia
Mon Mar 08 1999 - 13:12:11 PST
Support for values x and z
Jayaram Bhasker
Mon Mar 08 1999 - 15:16:51 PST
Re: Support for values x and z
Paul J. Menchini
Wed Mar 10 1999 - 06:14:42 PST
Re: Support for values x and z
Jayaram Bhasker
Wed Mar 10 1999 - 08:44:12 PST
Re: Support for values x and z
Clifford E. Cummings
Thu Mar 11 1999 - 11:28:02 PST
Review of Syntax section
Jayaram Bhasker
Fri Mar 12 1999 - 13:16:02 PST
Re: Call for DASC WG Nominations
Jayaram Bhasker
Thu Mar 25 1999 - 11:22:43 PST
Verilog Synthesis Working Group meeting: face to face
Jayaram Bhasker
Mon Mar 29 1999 - 05:21:34 PST
draft 1.3
Shalom Bresticker
Wed Mar 31 1999 - 13:08:47 PST
DASC member
Jayaram Bhasker
Thu Apr 01 1999 - 10:48:54 PST
Re: Verilog Synthesis Working Group meeting: face to face
Jayaram Bhasker
Thu Apr 01 1999 - 09:40:13 PST
NEW JOURNAL - CALL FOR PAPERS
Nikitas Assimakopoulos
Thu Apr 15 1999 - 21:30:13 PDT
Re: Modelling of level sensitive devices
Apurva Kalia
Fri Apr 23 1999 - 13:56:26 PDT
Meeting Minutes: P1364.1 Verilog Synthesis WG
Jayaram Bhasker
Fri Apr 23 1999 - 14:12:08 PDT
Compilation pragmas
Jayaram Bhasker
Fri Apr 23 1999 - 14:28:37 PDT
full_case, parallel_case
Jayaram Bhasker
Tue Apr 27 1999 - 12:42:56 PDT
Draft 1.4 Verilog RTL synthesis
Jayaram Bhasker
Tue Apr 27 1999 - 12:47:49 PDT
Next 1364.1 working group meeting
Jayaram Bhasker
Wed Apr 28 1999 - 08:18:37 PDT
Re: Compilation pragmas
Jayaram Bhasker
Thu May 06 1999 - 11:48:28 PDT
Re: Next 1364.1 working group meeting: REMINDER!!!!
Jayaram Bhasker
Fri May 07 1999 - 09:00:26 PDT
Functional Mismatches
Clifford E. Cummings
Fri May 07 1999 - 14:30:36 PDT
(no subject)
Cliff Cummings
Fri May 07 1999 - 14:31:00 PDT
Mismatch Paper PDF File - 2nd try
Cliff Cummings
Fri May 07 1999 - 14:41:10 PDT
BTF Conference Call - Verilog Attributes & Pragmas Discussion
Clifford E. Cummings
Mon May 10 1999 - 08:30:25 PDT
IEEE Fees??
Clifford E. Cummings
Mon May 10 1999 - 08:59:00 PDT
Re: IEEE Fees??
Clifford E. Cummings
Mon May 10 1999 - 09:19:51 PDT
Re: IEEE Fees??
Paul J. Menchini
Mon May 10 1999 - 13:41:48 PDT
DASC & SA Fees?
Clifford E. Cummings
Mon May 10 1999 - 14:07:40 PDT
Re: DASC & SA Fees?
Paul J. Menchini
Tue May 18 1999 - 17:25:16 PDT
Functional Mismatches Paper on the vlog-synth Web Site
Clifford E. Cummings
Tue May 25 1999 - 07:12:44 PDT
Comments on 1364.1 D1.4
Ken Coffman
Thu May 27 1999 - 03:44:25 PDT
Re: ! vs. ~
Shalom Bresticker
Wed Jun 16 1999 - 06:40:40 PDT
JASS Journal - Call for Papers
Nikitas Assimakopoulos
Tue Sep 14 1999 - 00:48:48 PDT
Special Issue of JASS Journal
Nikitas Assimakopoulos
Wed Oct 20 1999 - 04:06:36 PDT
DSD2000 Symposium, First Call for Papers
nunez@cma.ulpgc.es
Mon Dec 06 1999 - 02:45:07 PST
DDECS 2000 Call For Papers
lech@ics.ele.tue.nl
Fri Dec 10 1999 - 11:22:45 PST
International HDL Conference 2000 CALL FOR PAPERS
Jayaram Bhasker
Tue Feb 08 2000 - 10:13:34 PST
[Fwd: JOURNAL OF SYSTEMS ARCHITECTURE, Final Call For Papers]
David Bishop
Thu Jun 01 2000 - 05:01:33 PDT
OVI/Accellera Membership Rights
Jayaram Bhasker
Fri Sep 15 2000 - 10:57:29 PDT
[Fwd: Final Call for Papers, NOTE 9/22/00 deadline extension]
David Bishop
Tue Sep 26 2000 - 06:18:16 PDT
Here we go again ...
Jayaram Bhasker
Wed Sep 27 2000 - 06:32:54 PDT
verilog 2000 feature list
Jayaram Bhasker
Wed Sep 27 2000 - 08:51:09 PDT
RE: verilog 2000 feature list
Jayaram Bhasker
Wed Sep 27 2000 - 09:50:04 PDT
Re: verilog 2000 feature list
VhdlCohen@aol.com
Wed Sep 27 2000 - 12:27:50 PDT
problem with item 25
Stefen Boyd
Wed Sep 27 2000 - 12:59:52 PDT
Re: problem with item 25
Jayaram Bhasker
Wed Sep 27 2000 - 17:07:48 PDT
FWD: RE: verilog 2000 feature list
David Bishop
Mon Oct 16 2000 - 11:26:19 PDT
Re: SLR Balloting Feedback Request (fwd)
Jayaram Bhasker
Thu Oct 26 2000 - 16:32:48 PDT
Std P1364-Y2K :3.10 Arrays // Examples correct???
VhdlCohen@aol.com
Thu Oct 26 2000 - 16:32:39 PDT
Std P1364-Y2K : 3.9 Integers not regarded as hardware registers???
VhdlCohen@aol.com
Thu Oct 26 2000 - 17:50:11 PDT
RE: Std P1364-Y2K :3.10 Arrays // Examples correct???
Michael McNamara
Thu Oct 26 2000 - 18:17:11 PDT
Re: Std P1364-Y2K :3.10 Arrays // Examples correct???
VhdlCohen@aol.com
Fri Oct 27 2000 - 02:58:02 PDT
Re: Std P1364-Y2K :3.10 Arrays // Examples correct???
Shalom Bresticker
Wed Feb 07 2001 - 07:50:52 PST
Submission deadline extension for the Special Sessions on Modern Digital System Synthesis at SCI'2001]
David Bishop
Tue Feb 13 2001 - 10:39:51 PST
LRM 5.x: Unclear about when block refires on same event that changed
VhdlCohen@aol.com
Tue Feb 13 2001 - 11:27:07 PST
Re: LRM 5.x: Unclear about when block refires on same event that changed
M Ciletti
Tue Feb 13 2001 - 12:41:18 PST
Re: LRM 5.x: Unclear about when block refires on same event that changed
VhdlCohen@aol.com
Tue Feb 13 2001 - 20:24:31 PST
Re: LRM 5.x: Unclear about when block refires on same event that changed
M Ciletti
Wed Feb 14 2001 - 11:38:14 PST
Re: LRM 5.x: Unclear about when block refires on same event that changed
VhdlCohen@aol.com
Wed May 30 2001 - 06:09:43 PDT
Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01
J. Bhasker
Fri Jun 01 2001 - 11:12:47 PDT
Verilog2K synthesis features
J. Bhasker
Fri Jun 15 2001 - 08:41:23 PDT
New updated Verilog Synthesis draft, D1.6
J. Bhasker
Fri Jun 15 2001 - 08:54:38 PDT
Verilog2K synthesis features
J. Bhasker
Tue Jun 19 2001 - 13:03:23 PDT
Re: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01
J. Bhasker
Fri Jun 22 2001 - 09:24:23 PDT
Inferring ROMs in Verilog
VhdlCohen@aol.com
Sat Jun 23 2001 - 12:06:17 PDT
Re: Inferring RAMs in Verilog
VhdlCohen@aol.com
Fri Jun 29 2001 - 11:53:28 PDT
5.4 Modeling three-state drivers
VhdlCohen@aol.com
Tue Jul 03 2001 - 13:38:37 PDT
Using initialization statements for defining initial setup of registers
VhdlCohen@aol.com
Tue Jul 03 2001 - 16:13:19 PDT
Re: Using initialization statements for defining initial setup of registers
Clifford E. Cummings
Thu Jul 05 2001 - 09:01:02 PDT
Re: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01
Jayaram Bhasker
Thu Jul 05 2001 - 16:54:56 PDT
Re: Verilog Synthesis Interoperability Working Group: Agendafor July 6, '01
Praveen Tiwari
Fri Jul 06 2001 - 06:46:42 PDT
Re: Inferring ROMs in Verilog
Jayaram Bhasker
Fri Jul 06 2001 - 06:49:49 PDT
Re: Inferring RAMs in Verilog
Jayaram Bhasker
Fri Jul 06 2001 - 08:50:18 PDT
Re: Inferring ROMs in Verilog
Ken Coffman
Fri Jul 06 2001 - 08:58:42 PDT
Re: 5.4 Modeling three-state drivers
Ken Coffman
Fri Jul 06 2001 - 12:10:09 PDT
Paper on Verilog-2001 Enhancements
Clifford E. Cummings
Fri Jul 06 2001 - 12:57:21 PDT
vlog 2000 feature list
Jayaram Bhasker
Fri Jul 06 2001 - 19:05:11 PDT
Proposed styles for Inferring ROMs in Verilog
VhdlCohen@aol.com
Sat Jul 07 2001 - 15:51:26 PDT
Re: Inferring RAMs in Verilog
VhdlCohen@aol.com
Tue Jul 10 2001 - 06:51:56 PDT
Con Call MInutes, July 6, 2001
Ken Coffman
Tue Jul 10 2001 - 11:46:08 PDT
Re: Using initialization statements for defining initial setup of registers
Jayaram Bhasker
Tue Jul 10 2001 - 19:03:22 PDT
Re: Using initialization statements for defining initial setup of registers
VhdlCohen@aol.com
Wed Jul 11 2001 - 07:57:51 PDT
FDL 2001 Advance Program Announcement
Jayaram Bhasker
Tue Jul 10 2001 - 08:11:23 PDT
Re: Con Call MInutes, July 6, 2001
Shalom Bresticker (r50386)
Wed Jul 11 2001 - 10:04:27 PDT
Re: Proposed styles for Inferring ROMs in Verilog
Jayaram Bhasker
Wed Jul 11 2001 - 10:12:37 PDT
attributes
Joseph P. Wetstein
Wed Jul 11 2001 - 10:13:38 PDT
fullcase/parallel case (fwd)
Jayaram Bhasker
Wed Jul 11 2001 - 10:34:36 PDT
Re: fullcase/parallel case (fwd)
Joseph P. Wetstein
Wed Jul 11 2001 - 15:14:48 PDT
Re: Proposed styles for Inferring ROMs in Verilog
VhdlCohen@aol.com
Wed Jul 11 2001 - 19:16:38 PDT
Re: Proposed styles for Inferring ROMs in Verilog
VhdlCohen@aol.com
Wed Jul 11 2001 - 19:26:17 PDT
Re: Proposed styles for Inferring ROMs in Verilog
VhdlCohen@aol.com
Wed Jul 11 2001 - 02:43:35 PDT
Re: Con Call MInutes, July 6, 2001
Michael McNamara
Thu Jul 12 2001 - 11:12:32 PDT
Re: Proposed styles for Inferring ROMs in Verilog
VhdlCohen@aol.com
Sat Jul 14 2001 - 08:47:52 PDT
Inferring FPGA Hardware Features?
Ken Coffman
Sun Jul 15 2001 - 14:11:06 PDT
Re: Inferring FPGA Hardware Features?
VhdlCohen@aol.com
Mon Jul 16 2001 - 08:22:38 PDT
Re: Inferring FPGA Hardware Features?
Michael McNamara
Mon Jul 16 2001 - 10:05:01 PDT
Re: Inferring FPGA Hardware Features?
VhdlCohen@aol.com
Mon Jul 16 2001 - 10:14:31 PDT
Re: Inferring FPGA Hardware Features?
Michael McNamara
Mon Jul 16 2001 - 11:33:19 PDT
Draft Proposal: 5.6 Modeling Read-Only Memories (ROM); 5.7 RAM
VhdlCohen@aol.com
Tue Jul 17 2001 - 01:22:57 PDT
Re: Inferring FPGA Hardware Features?
Shalom Bresticker
Mon Jul 16 2001 - 14:41:12 PDT
Re: Inferring FPGA Hardware Features?
Michael McNamara
Tue Jul 17 2001 - 11:56:50 PDT
Re: Inferring FPGA Hardware Features?t
Joseph P. Wetstein
Tue Jul 17 2001 - 12:22:12 PDT
RE: Inferring FPGA Hardware Features?
Gilbert Nguyen
Thu Jul 19 2001 - 08:41:24 PDT
HDLCon 2002 Call for Papers
Jayaram Bhasker
Thu Jul 19 2001 - 09:11:34 PDT
RE: vlog 2000 feature list
Jayaram Bhasker
Thu Jul 19 2001 - 09:19:00 PDT
RE: vlog 2000 feature list
Jayaram Bhasker
Thu Jul 19 2001 - 09:52:56 PDT
constant function
Gilbert Nguyen
Thu Jul 19 2001 - 11:58:00 PDT
Re: constant function
Stefen Boyd
Fri Jul 20 2001 - 07:36:58 PDT
Re: constant function
Jayaram Bhasker
Fri Jul 20 2001 - 10:06:15 PDT
Re: constant function
Stefen Boyd
Fri Jul 20 2001 - 11:07:41 PDT
Re: constant function
Stefen Boyd
Fri Jul 20 2001 - 05:54:09 PDT
Re: constant function
Michael McNamara
Mon Aug 06 2001 - 08:49:31 PDT
Verilog Synthesis Interoperability Working Group Meeting: Agenda for Aug 10, '01
Jayaram Bhasker
Mon Aug 06 2001 - 14:40:00 PDT
Re: Assigning / testing different sizes -- shouldn't we restrict the use?
VhdlCohen@aol.com
Tue Aug 07 2001 - 16:10:04 PDT
Generate & defparams in Vlog-2001.
Krishna Garlapati
Wed Aug 08 2001 - 05:25:38 PDT
Re: Generate & defparams in Vlog-2001.
Shalom Bresticker
Wed Aug 08 2001 - 16:00:44 PDT
Re: Generate & defparams in Vlog-2001.
Krishna Garlapati
Wed Aug 08 2001 - 16:56:36 PDT
Re: Generate & defparams in Vlog-2001.
Stefen Boyd
Thu Aug 09 2001 - 02:26:54 PDT
Re: Generate & defparams in Vlog-2001.
Shalom Bresticker
Thu Aug 09 2001 - 09:19:09 PDT
Re: Generate & defparams in Vlog-2001.
Stefen Boyd
Thu Aug 09 2001 - 09:41:45 PDT
Re: Assigning / testing different sizes -- shouldn't we restrict the use?
VhdlCohen@aol.com
Thu Aug 09 2001 - 13:35:48 PDT
Re: Generate & defparams in Vlog-2001.
Krishna Garlapati
Thu Aug 09 2001 - 14:37:46 PDT
Re: Generate & defparams in Vlog-2001.
Stefen Boyd
Thu Aug 09 2001 - 15:06:59 PDT
Review of LRM sections for tomorrow's tele-conference
Sashi Obilisetty
Thu Aug 09 2001 - 15:28:57 PDT
Re: Generate & defparams in Vlog-2001.
Michael McNamara
Fri Aug 10 2001 - 10:56:21 PDT
RE: Verilog Synthesis Interoperability Working Group
Gilbert Nguyen
Fri Aug 10 2001 - 11:43:37 PDT
Proposal for ROM and RAM modeling Styles
VhdlCohen@aol.com
Fri Aug 10 2001 - 12:12:25 PDT
Re: Proposal for ROM and RAM modeling Styles
Stefen Boyd
Sun Aug 12 2001 - 20:49:15 PDT
Fwd: Proposal for ROM and RAM modeling Styles
VhdlCohen@aol.com
Wed Aug 22 2001 - 17:06:24 PDT
case-generate grammar issues.
Krishna Garlapati
Wed Aug 22 2001 - 20:17:11 PDT
Re: case-generate grammar issues.
Paul Graham
Thu Aug 23 2001 - 00:02:01 PDT
Re: case-generate grammar issues.
Krishna Garlapati
Thu Aug 23 2001 - 07:32:29 PDT
Re: case-generate grammar issues.
Paul Graham
Wed Aug 29 2001 - 17:04:40 PDT
V2K1 configs and lib map
Stefen Boyd
Thu Aug 30 2001 - 10:27:08 PDT
Verilog Synthesis Interoperability Working Group Meeting: Agenda for Sep 07, '01
Jayaram Bhasker
Sat Sep 01 2001 - 10:58:27 PDT
Navabi use of buried initial statement
Ken Coffman
Sun Sep 02 2001 - 03:00:42 PDT
Re: Navabi use of buried initial statement
Shalom Bresticker
Fri Sep 07 2001 - 11:01:15 PDT
Synthesis-related papers available for down-load
Clifford E. Cummings
Mon Sep 10 2001 - 12:40:46 PDT
Conference Call Minutes, Aug 10, 2001
Jayaram Bhasker
Thu Sep 13 2001 - 12:57:44 PDT
Romr/Ram spec comments
VhdlCohen@aol.com
Fri Sep 14 2001 - 07:20:02 PDT
Meeting minutes - Verilog Synthesis Working Group Meeting: Sept 7, 2001
Jayaram Bhasker
Sun Sep 23 2001 - 02:01:47 PDT
Synopsys support for Verilog-2001
Shalom Bresticker
Wed Sep 26 2001 - 11:07:50 PDT
Re: Synopsys support for Verilog-2001
J. Bhasker
Mon Oct 01 2001 - 08:41:34 PDT
Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01
J. Bhasker
Thu Oct 04 2001 - 19:20:06 PDT
[Fwd: Some comments on IEEE P1364.1/D1.7]
David Bishop
Fri Oct 05 2001 - 07:04:01 PDT
FW:
J. Bhasker
Fri Oct 05 2001 - 15:45:59 PDT
Verilog: ROMRAM Revision 2
VhdlCohen@aol.com
Fri Oct 05 2001 - 17:40:26 PDT
Initial Blocks fail with Synopsys Tools
Clifford E. Cummings
Sat Oct 06 2001 - 09:57:19 PDT
Re: Initial Blocks fail with Synopsys Tools
VhdlCohen@aol.com
Sat Oct 06 2001 - 10:14:40 PDT
Re: Verilog: ROMRAM Revision 2
VhdlCohen@aol.com
Sat Oct 06 2001 - 10:28:51 PDT
Re: Initial Blocks fail with Synopsys Tools
Jim Hudson
Mon Oct 08 2001 - 03:02:14 PDT
Re: Initial Blocks fail with Synopsys Tools
Ken Coffman
Mon Oct 08 2001 - 08:45:48 PDT
Re: Initial Blocks fail with Synopsys Tools
Paul Graham
Mon Oct 08 2001 - 10:07:23 PDT
RE: Initial Blocks fail with Synopsys Tools
Gilbert Nguyen
Mon Oct 08 2001 - 10:31:00 PDT
Re: Initial Blocks fail with Synopsys Tools
Krishna Garlapati
Mon Oct 08 2001 - 11:54:15 PDT
RE: Initial Blocks fail with Synopsys Tools
J. Bhasker
Mon Oct 08 2001 - 12:37:37 PDT
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01
J. Bhasker
Mon Oct 08 2001 - 12:53:45 PDT
For page 64, Section 4, example 4.4.3 -- value can't be verified
tiao@agere.com
Mon Oct 08 2001 - 12:57:53 PDT
example may be improved...
tiao@agere.com
Mon Oct 08 2001 - 13:04:20 PDT
Re: Initial Blocks fail with Synopsys Tools
Clifford E. Cummings
Mon Oct 08 2001 - 13:04:45 PDT
Incomplete Sensitivity Lists
Clifford E. Cummings
Mon Oct 08 2001 - 13:29:06 PDT
Re: Incomplete Sensitivity Lists
Paul Graham
Tue Oct 09 2001 - 13:38:16 PDT
[Fwd: Exemplar Handling of Initial Statement]
David Bishop
Tue Oct 09 2001 - 15:41:06 PDT
signed types & case statement expressions.
Krishna Garlapati
Tue Oct 09 2001 - 15:50:32 PDT
correction in my earlier email.
Krishna Garlapati
Tue Oct 09 2001 - 16:54:15 PDT
Re: signed types & case statement expressions.
Stefen Boyd
Thu Oct 11 2001 - 01:56:50 PDT
signed types
Muzaffer Kal
Thu Oct 11 2001 - 02:27:16 PDT
Re: signed types
Shalom Bresticker
Thu Oct 11 2001 - 11:48:55 PDT
RE: Verilog: ROMRAM Revision 2
J. Bhasker
Thu Oct 11 2001 - 13:25:33 PDT
Re: Verilog: ROMRAM Revision 2
VhdlCohen@aol.com
Thu Oct 11 2001 - 13:28:28 PDT
Re: Verilog: ROMRAM Revision 2
VhdlCohen@aol.com
Tue Oct 23 2001 - 11:50:56 PDT
Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
J. Bhasker
Wed Oct 24 2001 - 08:28:54 PDT
Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
Paul Graham
Wed Oct 24 2001 - 08:52:29 PDT
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
J. Bhasker
Wed Oct 24 2001 - 09:24:22 PDT
Attributes & Synthesis Pragmas
Clifford E. Cummings
Wed Oct 24 2001 - 10:22:28 PDT
Re: Attributes & Synthesis Pragmas
Joseph P. Wetstein
Wed Oct 24 2001 - 11:48:05 PDT
Re: Attributes & Synthesis Pragmas
Joseph P. Wetstein
Wed Oct 24 2001 - 12:43:31 PDT
Re: Attributes & Synthesis Pragmas
Krishna Garlapati
Wed Oct 24 2001 - 14:03:46 PDT
Re: Attributes and constant expressions
Stefen Boyd
Wed Oct 24 2001 - 14:39:11 PDT
Re: Attributes and constant expressions
Michael McNamara
Wed Oct 24 2001 - 14:51:28 PDT
Re: Attributes and constant expressions
Stefen Boyd
Wed Oct 24 2001 - 15:41:07 PDT
Re: Attributes and constant expressions
Michael McNamara
Wed Oct 24 2001 - 22:54:07 PDT
Re: Attributes and constant expressions
Shalom Bresticker
Wed Oct 24 2001 - 23:48:59 PDT
Re: Attributes & Synthesis Pragmas
Shalom Bresticker
Thu Oct 25 2001 - 06:13:30 PDT
RE: Attributes and constant expressions
J. Bhasker
Thu Oct 25 2001 - 06:20:56 PDT
RE: Attributes and constant expressions
J. Bhasker
Thu Oct 25 2001 - 06:53:12 PDT
RE: Attributes & Synthesis Pragmas
J. Bhasker
Thu Oct 25 2001 - 07:16:27 PDT
Re: Attributes and constant expressions
Shalom Bresticker
Thu Oct 25 2001 - 08:20:43 PDT
RE: Attributes and constant expressions
Michael McNamara
Thu Oct 25 2001 - 17:17:21 PDT
D1_7 Pragmas Proposal - Section 6 - 20011025
Clifford E. Cummings
Thu Nov 01 2001 - 06:06:29 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
J. Bhasker
Thu Nov 01 2001 - 10:25:24 PST
Minor corrections to IEEE P1364.1 / D1.7
VhdlCohen@aol.com
Thu Nov 01 2001 - 11:17:46 PST
Re: Minor corrections to IEEE P1364.1 / D1.7
Joseph P. Wetstein
Thu Nov 01 2001 - 11:35:29 PST
Re: Minor corrections to IEEE P1364.1 / D1.7
VhdlCohen@aol.com
Thu Nov 01 2001 - 12:19:54 PST
ROM definitions from within tasks and functions
VhdlCohen@aol.com
Thu Nov 01 2001 - 12:24:16 PST
Re: ROM definitions from within tasks and functions
Joseph P. Wetstein
Thu Nov 01 2001 - 14:42:22 PST
Re: ROM definitions from within tasks and functions
VhdlCohen@aol.com
Thu Nov 01 2001 - 18:30:41 PST
Re: D1_7 Pragmas Proposal - Section 6 - 20011025
Krishna Garlapati
Fri Nov 02 2001 - 06:07:26 PST
RE: Minor corrections to IEEE P1364.1 / D1.7
J. Bhasker
Fri Nov 02 2001 - 13:37:44 PST
New proposal for ROM definitions in functions and tasks
VhdlCohen@aol.com
Fri Nov 02 2001 - 14:53:53 PST
Re: New proposal for ROM definitions in functions and tasks
Stefen Boyd
Tue Nov 06 2001 - 11:27:28 PST
Meeting Minutes: Verilog Synthesis Interoperability Working Group Meeting on Nov 2, '01
J. Bhasker
Thu Nov 15 2001 - 15:12:42 PST
Re: New proposal for ROM definitions in functions and tasks
VhdlCohen@aol.com
Tue Nov 20 2001 - 17:02:31 PST
Re: New proposal for ROM definitions in functions and tasks
Clifford E. Cummings
Wed Nov 21 2001 - 07:09:27 PST
Re: New proposal for ROM definitions in functions and tasks
VhdlCohen@aol.com
Wed Nov 21 2001 - 10:09:30 PST
Re: New proposal for ROM definitions in functions and tasks
VhdlCohen@aol.com
Wed Nov 21 2001 - 10:12:34 PST
Re: New proposal for ROM definitions in functions and tasks
VhdlCohen@aol.com
Mon Dec 03 2001 - 10:54:50 PST
Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01
J. Bhasker
Thu Dec 06 2001 - 07:17:32 PST
D1_7 Pragmas Proposal - Section 6 - (updated 20011206)
Clifford E. Cummings
Fri Dec 07 2001 - 09:08:12 PST
Cadence (Ambit) pragmas
Paul Graham
Fri Dec 07 2001 - 16:21:35 PST
ROM RAM Update 12/07/01 + SYNP attributes
VhdlCohen@aol.com
Sun Dec 09 2001 - 00:58:42 PST
pragma suggestions
Muzaffer Kal
Sun Dec 09 2001 - 17:29:55 PST
Re: pragma suggestions
VhdlCohen@aol.com
Mon Dec 10 2001 - 00:18:21 PST
RE: pragma suggestions
Muzaffer Kal
Mon Dec 10 2001 - 14:29:47 PST
Re: pragma suggestions
VhdlCohen@aol.com
Mon Dec 10 2001 - 17:41:48 PST
Synplicity Pragmas for IEEE VLOG Synthesis standard
VhdlCohen@aol.com
Tue Dec 11 2001 - 09:56:59 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01
J. Bhasker
Tue Dec 11 2001 - 21:23:08 PST
VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper:
VhdlCohen@aol.com
Wed Dec 12 2001 - 06:26:58 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
VhdlCohen@aol.com
Wed Dec 12 2001 - 06:54:09 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
Shalom Bresticker
Wed Dec 12 2001 - 08:12:52 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
VhdlCohen@aol.com
Wed Dec 12 2001 - 10:54:32 PST
FYI: Initialization of RAM
VhdlCohen@aol.com
Wed Dec 12 2001 - 12:12:48 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
M Ciletti
Wed Dec 12 2001 - 13:45:33 PST
Fwd: Implicit FSMs style with mutiple clocks
VhdlCohen@aol.com
Wed Dec 12 2001 - 14:30:53 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
VhdlCohen@aol.com
Wed Dec 12 2001 - 16:17:16 PST
RE: FSM Enhancement Goals and Thoughts
Clifford E. Cummings
Wed Dec 12 2001 - 22:53:21 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
Shalom Bresticker
Thu Dec 13 2001 - 09:43:14 PST
Re: FSM Enhancement Goals and Thoughts
Clifford E. Cummings
Thu Dec 13 2001 - 11:35:31 PST
RE: FSM Enhancement Goals and Thoughts
J. Bhasker
Thu Dec 13 2001 - 14:22:55 PST
Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
VhdlCohen@aol.com
Fri Dec 14 2001 - 11:20:21 PST
FW: Fwd: Implicit FSMs style with mutiple clocks
J. Bhasker
Fri Dec 14 2001 - 23:31:11 PST
Re: Implicit FSMs style with mutiple clocks
VhdlCohen@aol.com
Mon Dec 17 2001 - 11:46:29 PST
new attribute (* synthesis, combinational *)
Stefen Boyd
Mon Dec 17 2001 - 12:23:58 PST
RE: new attribute (* synthesis, combinational *)
J. Bhasker
Mon Dec 17 2001 - 15:17:57 PST
RE: new attribute (* synthesis, combinational *)
Stefen Boyd
Tue Dec 18 2001 - 00:17:07 PST
Re: new attribute (* synthesis, combinational *)
Shalom Bresticker
Tue Dec 18 2001 - 02:42:07 PST
pragmas
Shalom Bresticker
Tue Dec 18 2001 - 06:21:38 PST
Re: pragmas
Paul Graham
Tue Dec 18 2001 - 06:27:16 PST
Re: pragmas
Shalom Bresticker
Tue Dec 18 2001 - 07:12:50 PST
RE: pragmas
Michael McNamara
Tue Dec 18 2001 - 07:12:56 PST
Re: pragmas
Paul Graham
Tue Dec 18 2001 - 07:19:45 PST
Re: pragmas
Daryl Stewart
Tue Dec 18 2001 - 08:07:28 PST
Re: pragmas
Shalom Bresticker
Tue Dec 18 2001 - 08:25:47 PST
Re: pragmas
Shalom Bresticker
Tue Dec 18 2001 - 08:58:58 PST
Re: D1_7 Pragmas Proposal - Section 6 - (updated 20011206)
Shalom Bresticker
Tue Dec 18 2001 - 09:02:36 PST
Re: pragmas
Daryl Stewart
Tue Dec 18 2001 - 09:30:02 PST
RE: D1_7 Pragmas Proposal - Section 6 - (updated 20011206)
J. Bhasker
Thu Jan 03 2002 - 11:02:29 PST
FW: 1364.1 draft 1.8
J. Bhasker
Tue Jan 08 2002 - 06:19:28 PST
Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
J. Bhasker
Thu Jan 10 2002 - 13:52:59 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
J. Bhasker
Thu Jan 10 2002 - 18:29:16 PST
Synplify attributes.
Krishna Garlapati
Thu Jan 10 2002 - 20:20:56 PST
Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
Paul Graham
Fri Jan 11 2002 - 06:20:19 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
J. Bhasker
Fri Jan 11 2002 - 07:31:03 PST
Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
Paul Graham
Fri Jan 11 2002 - 08:51:30 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
Gilbert Nguyen
Fri Jan 11 2002 - 09:47:51 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
Muzaffer Kal
Fri Jan 11 2002 - 10:40:22 PST
Re: Asynchronous design
VhdlCohen@aol.com
Fri Jan 11 2002 - 10:58:58 PST
reminder of the word "directives" used in the draft...
Jenjen_Tiao
Fri Jan 11 2002 - 12:44:17 PST
Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
Paul Graham
Sun Jan 13 2002 - 15:30:37 PST
Verilog Black-Box Sample Model // + EDIF
VhdlCohen@aol.com
Wed Jan 16 2002 - 08:28:40 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
J. Bhasker
Wed Jan 16 2002 - 11:33:20 PST
RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
J. Bhasker
Wed Jan 16 2002 - 11:34:16 PST
Blackbox attribute
VhdlCohen@aol.com
Tue Jan 22 2002 - 14:04:19 PST
Attribute "encoding"
Jayaram Bhasker
Tue Jan 22 2002 - 15:47:11 PST
Re: Attribute "encoding"
VhdlCohen@aol.com
Wed Jan 30 2002 - 15:45:11 PST
Draft 1.9 // synthesis encoding vs state_machine
VhdlCohen@aol.com
Wed Jan 30 2002 - 15:45:14 PST
(* synthesis, keep [=<optional_value>] *)
VhdlCohen@aol.com
Wed Jan 30 2002 - 16:48:15 PST
Re: (* synthesis, keep [=<optional_value>] *)
Krishna Garlapati
Wed Jan 30 2002 - 17:15:19 PST
Re: (* synthesis, keep [=<optional_value>] *)
VhdlCohen@aol.com
Wed Jan 30 2002 - 18:15:25 PST
Re: (* synthesis, keep [=<optional_value>] *)
Krishna Garlapati
Thu Jan 31 2002 - 08:43:35 PST
RE: (* synthesis, keep [=<optional_value>] *)
Muzaffer Kal
Thu Jan 31 2002 - 08:35:55 PST
Re: (* synthesis, keep [=<optional_value>] *)
VhdlCohen@aol.com
Thu Jan 31 2002 - 09:19:26 PST
RE: (* synthesis, keep [=<optional_value>] *)
Muzaffer Kal
Thu Jan 31 2002 - 09:12:58 PST
Re: (* synthesis, keep [=<optional_value>] *)
VhdlCohen@aol.com
Thu Jan 31 2002 - 10:19:14 PST
RE: Draft 1.9 // synthesis encoding vs state_machine
Jayaram Bhasker
Thu Jan 31 2002 - 10:39:01 PST
Re: Draft 1.9 // synthesis encoding vs state_machine
VhdlCohen@aol.com
Fri Feb 01 2002 - 01:55:26 PST
RE: Draft 1.9 // synthesis encoding vs state_machine
Shalom.Bresticker@motorola.com
Fri Feb 01 2002 - 11:42:53 PST
RE: (* synthesis, keep [=<optional_value>] *)
Jayaram Bhasker
Fri Feb 01 2002 - 12:15:31 PST
Re: (* synthesis, keep [=<optional_value>] *)
VhdlCohen@aol.com
Mon Feb 04 2002 - 11:13:19 PST
Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002
Jayaram Bhasker
Fri Feb 08 2002 - 06:09:20 PST
RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002
Jayaram Bhasker
Fri Feb 08 2002 - 08:46:52 PST
Re: (* synthesis, keep [=<optional_value>] *) // ALL?
VhdlCohen@aol.com
Fri Feb 08 2002 - 11:57:19 PST
RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES
Jayaram Bhasker
Fri Feb 08 2002 - 13:37:50 PST
RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES
Jayaram Bhasker
Tue Feb 12 2002 - 08:24:12 PST
FW: Invitation to Ballot for P1364.1
Jayaram Bhasker
Wed Feb 13 2002 - 06:16:14 PST
FW: Verilog Synthesis draft 2.0
Jayaram Bhasker
Sun Feb 17 2002 - 13:35:57 PST
Verilog Synthesis draft 2.0 // Comments
VhdlCohen@aol.com
Mon Feb 25 2002 - 06:32:50 PST
RE: Verilog Synthesis draft 2.0 // Comments
Jayaram Bhasker
Mon Feb 25 2002 - 10:31:28 PST
Re: Verilog Synthesis draft 2.0 // Comments // Krishna RSVP
VhdlCohen@aol.com
Mon Feb 25 2002 - 11:42:34 PST
Re: Verilog Synthesis draft 2.0 // Comments // Krishna RSVP
Krishna Garlapati
Tue Feb 26 2002 - 09:54:24 PST
FW: Editorial coordination on draft 1364.1
Jayaram Bhasker
Thu Feb 28 2002 - 12:07:27 PST
Some review comments
Jayaram Bhasker
Fri Mar 01 2002 - 11:53:03 PST
Annex B Replacement Proposal
Clifford E. Cummings
Mon Mar 04 2002 - 13:23:59 PST
RE: Annex B Replacement Proposal
Jayaram Bhasker
Wed Mar 06 2002 - 07:20:47 PST
1364.1 WG meeting at HDLCON
Jayaram Bhasker
Wed Mar 06 2002 - 09:27:17 PST
Keep Attribute // An update
VhdlCohen@aol.com
Wed Mar 06 2002 - 11:24:21 PST
1364.1 WG meeting at HDLCON
Jayaram Bhasker
Fri Mar 08 2002 - 14:42:53 PST
recursive instantiations of modules
VhdlCohen@aol.com
Fri Mar 08 2002 - 15:12:19 PST
Re: recursive instantiations of modules
Paul Graham
Fri Mar 08 2002 - 19:10:43 PST
Re: recursive instantiations of modules
M Ciletti
Sun Mar 10 2002 - 07:32:47 PST
Re: recursive instantiations of modules
Shalom Bresticker
Sun Mar 10 2002 - 14:28:38 PST
Re: recursive instantiations of modules
M Ciletti
Sun Mar 10 2002 - 14:30:22 PST
Re: recursive instantiations of modules
M Ciletti
Sun Mar 10 2002 - 14:38:54 PST
Re: recursive instantiations of modules - MORE
M Ciletti
Sun Mar 10 2002 - 15:15:45 PST
RE: recursive instantiations of modules
Muzaffer Kal
Mon Mar 11 2002 - 01:25:19 PST
Re: recursive instantiations of modules
Shalom Bresticker
Mon Mar 11 2002 - 05:46:38 PST
Re: recursive instantiations of modules
M Ciletti
Mon Mar 11 2002 - 05:56:51 PST
Re: recursive instantiations of modules
Shalom Bresticker
Mon Mar 11 2002 - 07:39:34 PST
Re: recursive instantiations of modules
M Ciletti
Mon Mar 11 2002 - 08:13:51 PST
Re: recursive instantiations of modules - MORE
Paul Graham
Fri Mar 15 2002 - 13:47:24 PST
Verilog Synthesis WG Meeting minutes: March 11, 2002
Jayaram Bhasker
Sun Mar 17 2002 - 07:56:51 PST
Re: Assignments in the Verilog RTL Synthesizes draft
Clifford E. Cummings
Mon Mar 18 2002 - 12:52:10 PST
Verilog Synthesis Interoperability WG: NO MEETING ON MARCH 22
Jayaram Bhasker
Tue Mar 19 2002 - 08:59:57 PST
Tri-state push thru
VhdlCohen@aol.com
Mon Mar 25 2002 - 14:22:17 PST
RE: Assignments in the Verilog RTL Synthesizes draft
Jayaram Bhasker
Wed Mar 27 2002 - 08:27:09 PST
Another attribute: test_port
Jayaram Bhasker
Wed Mar 27 2002 - 09:07:16 PST
Re: Another attribute: test_port
VhdlCohen@aol.com
Thu Mar 28 2002 - 01:08:28 PST
assigning 'X'
Muzaffer Kal
Thu Mar 28 2002 - 01:09:23 PST
RE: Another attribute: test_port
Muzaffer Kal
Thu Mar 28 2002 - 01:15:28 PST
correction to section 5.4
Muzaffer Kal
Thu Mar 28 2002 - 10:38:43 PST
Re: Another attribute: test_port
VhdlCohen@aol.com
Thu Mar 28 2002 - 11:12:32 PST
Re: Another attribute: test_port
VhdlCohen@aol.com
Fri Mar 29 2002 - 07:47:59 PST
Updated 1364.1 v2.1 draft available
Jayaram Bhasker
Fri Mar 29 2002 - 07:53:58 PST
Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02
Jayaram Bhasker
Fri Mar 29 2002 - 12:45:07 PST
attribute: test_port // more comments
VhdlCohen@aol.com
Fri Mar 29 2002 - 12:53:14 PST
6.1 Synthesis attributes // minor syntax update
VhdlCohen@aol.com
Fri Mar 29 2002 - 14:52:51 PST
1364.1 v2.1 draft COMMENTS
VhdlCohen@aol.com
Wed Apr 03 2002 - 03:50:37 PST
Re: 6.1 Synthesis attributes // minor syntax update
Daryl Stewart
Wed Apr 03 2002 - 04:38:12 PST
Re: attribute: test_port // more comments
Daryl Stewart
Wed Apr 03 2002 - 12:20:31 PST
Re: 6.1 Synthesis attributes // minor syntax update
VhdlCohen@aol.com
Wed Apr 03 2002 - 12:31:53 PST
Re: attribute: test_port // more comments
VhdlCohen@aol.com
Thu Apr 04 2002 - 03:44:49 PST
Re: attribute: test_port // more comments
Daryl Stewart
Thu Apr 04 2002 - 12:37:11 PST
RE: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02
Jayaram Bhasker
Thu Apr 04 2002 - 17:54:55 PST
Re: attribute: test_port // more comments
VhdlCohen@aol.com
Fri Apr 05 2002 - 05:45:38 PST
Re: attribute: test_port // new text proposal
Daryl Stewart
Fri Apr 05 2002 - 14:42:49 PST
section 5.6 ROM // Question
VhdlCohen@aol.com
Fri Apr 05 2002 - 15:51:35 PST
Re: section 5.6 ROM // Question
VhdlCohen@aol.com
Mon Apr 08 2002 - 06:41:14 PDT
RE: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02
Jayaram Bhasker
Wed Apr 10 2002 - 16:02:43 PDT
Section 7.7.9.1 - Initial Blocks - Illegal??
Clifford E. Cummings
Wed Apr 10 2002 - 16:13:59 PDT
Re: Section 7.7.9.1 - Initial Blocks - Illegal??
Paul Graham
Wed Apr 10 2002 - 17:39:15 PDT
Re: Section 7.7.9.1 - Initial Blocks - Illegal??
Clifford E. Cummings
Wed Apr 10 2002 - 23:28:21 PDT
Re: Section 7.7.9.1 - Initial Blocks - Illegal??
Shalom.Bresticker@motorola.com
Thu Apr 11 2002 - 09:15:54 PDT
Re: Section 7.7.9.1 - Initial Blocks - Illegal??
Clifford E. Cummings
Thu Apr 11 2002 - 12:13:20 PDT
Proposed BNF Fix for Verilog-2001 Parameter Errata
Clifford E. Cummings
Thu Apr 11 2002 - 14:08:11 PDT
Re: Proposed BNF Fix for Verilog-2001 Parameter Errata
Pat Bryant
Thu Apr 11 2002 - 14:34:12 PDT
Re: Proposed BNF Fix for Verilog-2001 Parameter Errata
Clifford E. Cummings
Thu Apr 11 2002 - 14:30:33 PDT
Re: Proposed BNF Fix for Verilog-2001 Parameter Errata
Clifford E. Cummings
Fri Apr 12 2002 - 06:26:49 PDT
RE: Proposed BNF Fix for Verilog-2001 Parameter Errata
Jayaram Bhasker
Fri Apr 12 2002 - 09:40:55 PDT
Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Clifford E. Cummings
Fri Apr 12 2002 - 19:53:37 PDT
Floating point synthesis, call for participation
David Bishop
Sun Apr 14 2002 - 07:58:10 PDT
Re: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Shalom.Bresticker@motorola.com
Mon Apr 15 2002 - 14:46:40 PDT
PASSED (SystemVerilog) - ANSI-Style Parameter Port List BNF Correction
Clifford E. Cummings
Mon Apr 15 2002 - 14:48:13 PDT
Re: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Clifford E. Cummings
Mon Apr 15 2002 - 20:29:50 PDT
Re: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Ken Coffman
Mon Apr 15 2002 - 22:12:20 PDT
RE: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Muzaffer Kal
Tue Apr 16 2002 - 08:49:32 PDT
RE: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Stefen Boyd
Tue Apr 16 2002 - 11:23:45 PDT
RE: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
Jayaram Bhasker
Thu Apr 25 2002 - 06:22:07 PDT
RE: section 5.6 ROM // Question
Jayaram Bhasker
Thu Apr 25 2002 - 13:27:24 PDT
Draft D2.2 for ballot
Jayaram Bhasker
Fri Apr 26 2002 - 06:44:11 PDT
RE: Draft D2.2 for ballot
Jayaram Bhasker
Mon Apr 29 2002 - 22:49:15 PDT
Re: assigning 'X'
Shalom Bresticker
Sun May 05 2002 - 01:16:17 PDT
Re: assigning 'X'
Shalom Bresticker
Wed May 15 2002 - 13:02:53 PDT
1364.1 in ballot
Jayaram Bhasker
Wed Jun 12 2002 - 14:36:21 PDT
Please vote yes - 1364.1 ballot
Clifford E. Cummings
Wed Jun 12 2002 - 17:39:31 PDT
Re: Please vote yes - 1364.1 ballot
Clifford E. Cummings
Wed Jun 12 2002 - 17:54:59 PDT
Re: Please vote yes - 1364.1 ballot
David Bishop
Thu Jun 13 2002 - 13:35:24 PDT
Re: Looking for peace in the VHDL and Verilog Attributes
John Michael Williams
Thu Jun 13 2002 - 14:00:10 PDT
Re: Looking for peace in the VHDL and Verilog Attributes
Paul Graham
Thu Jun 13 2002 - 14:27:48 PDT
Re: Looking for peace in the VHDL and Verilog Attributes
Clifford E. Cummings
Fri Jun 14 2002 - 10:41:10 PDT
Re: Please vote yes - 1364.1 ballot
Paul J. Menchini
Fri Jun 14 2002 - 11:40:42 PDT
Re: Please vote yes - 1364.1 ballot
Clifford E. Cummings
Fri Jun 14 2002 - 12:02:37 PDT
Re: Please vote yes - 1364.1 ballot
Paul J. Menchini
Mon Jun 17 2002 - 09:59:35 PDT
Re: Looking for peace in the VHDL and Verilog Attributes
Michael McNamara
Wed Jun 26 2002 - 08:12:10 PDT
Verilog RTL Synthesis ballot passes!
Jbhasker7@aol.com
Wed Jun 26 2002 - 09:16:33 PDT
RE: Verilog RTL Synthesis ballot passes!
Michael McNamara
Wed Jun 26 2002 - 10:08:52 PDT
Re: Verilog RTL Synthesis ballot passes!
Clifford E. Cummings
Thu Jun 27 2002 - 08:42:45 PDT
Re: Verilog RTL Synthesis ballot passes!
Jbhasker7@aol.com
Mon Jul 01 2002 - 12:22:11 PDT
Re: Verilog RTL Synthesis ballot passes!
Paul J. Menchini
Sat Jul 06 2002 - 13:39:02 PDT
synthesis attribute question
Muzaffer Kal
Sun Jul 07 2002 - 08:05:26 PDT
Re: synthesis attribute question
Shalom Bresticker
Sat Jul 13 2002 - 11:35:34 PDT
Question on ROM // Your opinion on reply
VhdlCohen@aol.com
Sat Jul 13 2002 - 12:17:34 PDT
Re: Question on ROM // Your opinion on reply
VhdlCohen@aol.com
Sat Jul 13 2002 - 12:26:12 PDT
Re: Question on ROM // Your opinion on reply
John Michael Williams
Sat Jul 13 2002 - 12:44:08 PDT
Re: Question on ROM // Your opinion on reply
VhdlCohen@aol.com
Mon Jul 15 2002 - 06:14:19 PDT
Re: Question on ROM // Your opinion on reply
Jbhasker7@aol.com
Mon Jul 15 2002 - 07:59:49 PDT
Re: Question on ROM // Your opinion on reply
Shalom Bresticker
Mon Jul 15 2002 - 12:46:52 PDT
Ballot feedback: test_port
Jbhasker7@aol.com
Mon Jul 15 2002 - 12:57:59 PDT
Ballot comment: multiplication
Jbhasker7@aol.com
Mon Jul 15 2002 - 13:52:46 PDT
Re: Ballot comment: multiplication
John Michael Williams
Mon Jul 15 2002 - 16:40:32 PDT
re: Ballot feedback: test_port
VhdlCohen@aol.com
Tue Jul 16 2002 - 10:28:46 PDT
Re: Ballot feedback: test_port
Steve Golson
Tue Jul 16 2002 - 10:48:35 PDT
Re: Ballot comment: multiplication
Jenjen_Tiao
Thu Aug 08 2002 - 03:06:16 PDT
vector bit-select in sensitivity list
Shalom Bresticker
Thu Aug 08 2002 - 09:29:07 PDT
RE: vector bit-select in sensitivity list
Michael McNamara
Thu Aug 08 2002 - 10:47:50 PDT
Re: vector bit-select in sensitivity list
Steve Golson
Thu Aug 08 2002 - 13:07:34 PDT
Re: vector bit-select in sensitivity list
Michael McNamara
Thu Aug 08 2002 - 18:35:26 PDT
Re: vector bit-select in sensitivity list
Steve Golson
Thu Aug 08 2002 - 20:13:32 PDT
Re: vector bit-select in sensitivity list
Paul Graham
Thu Aug 08 2002 - 22:25:01 PDT
RE: vector bit-select in sensitivity list
Shalom.Bresticker@motorola.com
Fri Aug 09 2002 - 03:09:03 PDT
Re: vector bit-select in sensitivity list
Shalom.Bresticker@motorola.com
Fri Aug 09 2002 - 06:12:47 PDT
Re: vector bit-select in sensitivity list
Steve Golson
Fri Aug 09 2002 - 07:42:05 PDT
Re: vector bit-select in sensitivity list
Paul Graham
Fri Aug 09 2002 - 07:45:20 PDT
Re: vector bit-select in sensitivity list
Paul Graham
Sat Aug 10 2002 - 22:03:03 PDT
Re: vector bit-select in sensitivity list
Shalom Bresticker
Mon Aug 19 2002 - 06:38:48 PDT
Ballot response document
Jayaram Bhasker
Wed Aug 21 2002 - 08:27:30 PDT
FW: Ballot response document
Jayaram Bhasker
Wed Aug 21 2002 - 13:25:11 PDT
feedback for the ballot response document
Jenjen Tiao
Thu Aug 22 2002 - 01:18:49 PDT
Re: feedback for the ballot response document
Shalom Bresticker
Mon Aug 26 2002 - 05:43:27 PDT
1364.1 ballot responses
Shalom.Bresticker@motorola.com
Mon Aug 26 2002 - 06:09:06 PDT
Re: 1364.1 ballot responses
Daryl Stewart
Mon Aug 26 2002 - 06:46:40 PDT
Making ballot responses consistent
Jayaram Bhasker
Mon Aug 26 2002 - 07:24:42 PDT
Re: 1364.1 ballot responses
Shalom Bresticker
Mon Aug 26 2002 - 13:13:29 PDT
RE: feedback for the ballot response document
Jayaram Bhasker
Mon Aug 26 2002 - 22:15:52 PDT
Re: feedback for the ballot response document
Shalom Bresticker
Wed Aug 28 2002 - 01:02:40 PDT
1364.1 pragmas
Shalom Bresticker
Wed Aug 28 2002 - 01:12:48 PDT
1364.1: ROM and RAM modeling
Shalom Bresticker
Wed Aug 28 2002 - 06:23:56 PDT
1364.1 comments
Shalom Bresticker
Wed Aug 28 2002 - 08:22:03 PDT
RE: 1364.1 pragmas
Michael McNamara
Wed Aug 28 2002 - 09:02:08 PDT
RE: feedback for the ballot response document
Jayaram Bhasker
Wed Aug 28 2002 - 09:49:14 PDT
RE: 1364.1 ballot responses
Jayaram Bhasker
Wed Aug 28 2002 - 10:18:39 PDT
RE: feedback for the ballot response document
Sampath Prithivadhi Bayankaram
Wed Aug 28 2002 - 11:58:57 PDT
RE: feedback for the ballot response document
Shalom.Bresticker@motorola.com
Wed Aug 28 2002 - 15:51:46 PDT
RE: 1364.1 pragmas
Clifford E. Cummings
Wed Aug 28 2002 - 16:21:02 PDT
RE: 1364.1 pragmas
Michael McNamara
Wed Aug 28 2002 - 17:28:31 PDT
RE: 1364.1 pragmas
Clifford E. Cummings
Wed Aug 28 2002 - 19:06:07 PDT
Re: 1364.1 pragmas
Paul Graham
Thu Aug 29 2002 - 01:12:25 PDT
Re: 1364.1 ballot responses
Shalom Bresticker
Thu Aug 29 2002 - 01:44:23 PDT
Re: 1364.1 pragmas
Shalom Bresticker
Thu Aug 29 2002 - 01:52:31 PDT
Re: 1364.1 pragmas
Shalom Bresticker
Thu Aug 29 2002 - 06:07:30 PDT
RE: 1364.1 pragmas
David Bishop
Thu Aug 29 2002 - 07:47:57 PDT
Re: 1364.1 pragmas
John Michael Williams
Thu Aug 29 2002 - 08:01:27 PDT
Re: feedback for the ballot response document
Shalom Bresticker
Thu Aug 29 2002 - 08:55:35 PDT
RE: 1364.1 pragmas
Jayaram Bhasker
Thu Aug 29 2002 - 10:40:10 PDT
Re: 1364.1 ballot responses
Steve Golson
Thu Aug 29 2002 - 15:09:42 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Thu Aug 29 2002 - 15:53:49 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Thu Aug 29 2002 - 16:37:55 PDT
Re: 1364.1 pragmas
John Michael Williams
Thu Aug 29 2002 - 23:11:43 PDT
Re: 1364.1 pragmas
Shalom.Bresticker@motorola.com
Thu Aug 29 2002 - 23:14:41 PDT
Re: 1364.1 pragmas
Shalom.Bresticker@motorola.com
Fri Aug 30 2002 - 08:29:24 PDT
Re: 1364.1 pragmas
Michael McNamara
Fri Aug 30 2002 - 10:01:04 PDT
Re: 1364.1 pragmas
John Michael Williams
Fri Aug 30 2002 - 13:07:11 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Fri Aug 30 2002 - 13:24:22 PDT
Re: 1364.1 pragmas
Paul Graham
Fri Aug 30 2002 - 13:42:14 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Fri Aug 30 2002 - 15:51:00 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Fri Aug 30 2002 - 16:22:08 PDT
Re: 1364.1 pragmas
John Michael Williams
Fri Aug 30 2002 - 16:25:37 PDT
Re: 1364.1 pragmas
Michael McNamara
Fri Aug 30 2002 - 16:51:23 PDT
RE: 1364.1 pragmas
Erich Marschner
Fri Aug 30 2002 - 19:20:30 PDT
Re: 1364.1 pragmas
Paul Graham
Mon Sep 02 2002 - 02:22:13 PDT
Re: 1364.1 pragmas
Shalom Bresticker
Mon Sep 02 2002 - 12:13:06 PDT
Re: 1364.1 pragmas
David Bishop
Mon Sep 02 2002 - 12:20:06 PDT
Re: 1364.1 pragmas
David Bishop
Mon Sep 02 2002 - 12:26:23 PDT
Re: 1364.1 pragmas
David Bishop
Mon Sep 02 2002 - 12:37:38 PDT
Re: 1364.1 pragmas
David Bishop
Mon Sep 02 2002 - 12:39:09 PDT
Re: 1364.1 pragmas
David Bishop
Mon Sep 02 2002 - 13:03:02 PDT
Re: 1364.1 pragmas
David Bishop
Mon Sep 02 2002 - 13:04:20 PDT
Re: 1364.1 pragmas
David Bishop
Tue Sep 03 2002 - 05:49:43 PDT
Re: 1364.1 pragmas
David Bishop
Tue Sep 03 2002 - 09:48:34 PDT
Re: 1364.1 pragmas
John Michael Williams
Tue Sep 03 2002 - 13:09:54 PDT
Fw: 1364.1 pragmas
Pat Bryant
Tue Sep 03 2002 - 16:37:45 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Tue Sep 03 2002 - 16:40:49 PDT
Re: 1364.1 pragmas
David Bishop
Tue Sep 03 2002 - 16:58:28 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Tue Sep 03 2002 - 18:43:52 PDT
RE: 1364.1 pragmas
Jayaram Bhasker
Tue Sep 03 2002 - 19:33:31 PDT
Re: 1364.1 pragmas
Paul Graham
Tue Sep 03 2002 - 23:18:36 PDT
Re: Fw: 1364.1 pragmas
John Michael Williams
Wed Sep 04 2002 - 04:33:19 PDT
[Fwd: BOUNCE vlog-synth@eda.org: Non-member submission from[Daryl.Stewart@tenisontech.com]]
David Bishop
Wed Sep 04 2002 - 04:34:42 PDT
Re: 1364.1 pragmas
David Bishop
Wed Sep 04 2002 - 05:05:17 PDT
Re: 1364.1 pragmas
David Bishop
Wed Sep 04 2002 - 18:31:51 PDT
Re: 1364.1 pragmas
David Bishop
Fri Sep 06 2002 - 07:23:57 PDT
RE: 1364.1 pragmas
Jayaram Bhasker
Fri Sep 06 2002 - 09:21:34 PDT
RE: 1364.1 pragmas
Stefen Boyd
Fri Sep 06 2002 - 09:13:42 PDT
RE: 1364.1 pragmas
Stefen Boyd
Fri Sep 06 2002 - 09:37:08 PDT
RE: 1364.1 pragmas
Michael McNamara
Fri Sep 06 2002 - 11:06:11 PDT
RE: 1364.1 pragmas
Jayaram Bhasker
Fri Sep 06 2002 - 11:35:53 PDT
RE: 1364.1 pragmas
Jayaram Bhasker
Wed Sep 11 2002 - 07:34:41 PDT
1364.1 recirculation ballot
Jayaram Bhasker
Wed Sep 11 2002 - 07:59:05 PDT
Re: 1364.1 recirculation ballot
Shalom Bresticker
Thu Sep 12 2002 - 05:26:37 PDT
RE: 1364.1 recirculation ballot
Jayaram Bhasker
Fri Sep 20 2002 - 10:13:54 PDT
RE: 1364.1 pragmas
Clifford E. Cummings
Fri Sep 20 2002 - 15:17:51 PDT
RE: 1364.1 pragmas
Steven Sharp
Mon Sep 30 2002 - 06:10:25 PDT
1364.1 passes second recirculation ballot
Jayaram Bhasker
Mon Sep 30 2002 - 07:44:29 PDT
Re: 1364.1 passes second recirculation ballot
Paul J. Menchini
Tue Oct 01 2002 - 00:48:15 PDT
Comments on P1364.1/Draft 2.3
Shalom Bresticker
Thu Oct 03 2002 - 06:40:44 PDT
Comments on P1364.1/Draft 2.3, Clause 5
Shalom Bresticker
Thu Oct 03 2002 - 08:05:33 PDT
Comments on P1364.1/Draft 2.3, Clause 5
Shalom Bresticker
Fri Oct 04 2002 - 02:16:59 PDT
Re: Comments on P1364.1/Draft 2.3, Clause 5
Shalom.Bresticker@motorola.com
Sun Oct 06 2002 - 02:25:49 PDT
Comments on P1364.1/Draft 2.3, Clause 6
Shalom.Bresticker@motorola.com
Sun Oct 06 2002 - 02:32:01 PDT
6.3.2
Shalom.Bresticker@motorola.com
Wed Oct 09 2002 - 13:06:44 PDT
Re: 1364.1 pragmas
John Michael Williams
Wed Oct 09 2002 - 13:50:02 PDT
Re: 1364.1 pragmas
Paul Graham
Wed Oct 09 2002 - 15:15:36 PDT
Re: 1364.1 pragmas
Clifford E. Cummings
Wed Oct 09 2002 - 15:51:18 PDT
Re: 1364.1 pragmas
Michael McNamara
Wed Oct 09 2002 - 19:57:17 PDT
Re: 1364.1 pragmas
John Michael Williams
Wed Oct 09 2002 - 20:24:13 PDT
Re: 1364.1 pragmas
Paul Graham
Thu Oct 10 2002 - 09:30:40 PDT
Re: 1364.1 pragmas
Michael McNamara
Fri Oct 18 2002 - 17:59:37 PDT
Suggestions for synthesis tools
VhdlCohen@aol.com
Fri Oct 18 2002 - 20:33:06 PDT
Re: Suggestions for synthesis tools
John Michael Williams
Fri Oct 18 2002 - 20:47:46 PDT
Re: Suggestions for synthesis tools
Paul Graham
Tue Oct 22 2002 - 07:31:27 PDT
Attribute KEEP vs NO_DUPLICATE & "clock uncertainty".
VhdlCohen@aol.com
Mon Dec 16 2002 - 05:12:08 PST
Verilog RTL Synthesis: It is a standard! It is a standard! An IEEE Standard!
Jayaram Bhasker
Wed Dec 18 2002 - 12:14:32 PST
Verilog RTL Synthesis standard: complimentary copy
Jayaram Bhasker
Wed Dec 18 2002 - 19:52:22 PST
Re: Verilog RTL Synthesis standard: complimentary copy
Vinaya Singh
Wed Dec 18 2002 - 20:11:27 PST
Re: Verilog RTL Synthesis standard: complimentary copy
Vinaya Singh
Wed Jan 08 2003 - 12:50:47 PST
FW: SLR Invitation to ballot on P260.1-SCC14 (fwd)
Jayaram Bhasker
Thu Mar 13 2003 - 14:55:49 PST
[vlog-synth] Call for Contributions FDL 2003
David Bishop
Tue Mar 18 2003 - 11:45:38 PST
[vlog-synth] FDL'03
David Bishop
Tue Jun 10 2003 - 10:10:50 PDT
[vlog-synth] FW: Electronic Standards Delivery Issue
Jayaram Bhasker
Tue Jul 01 2003 - 07:55:57 PDT
[vlog-synth] DVCon 2004 Call For Papers
Jayaram Bhasker
Fri Nov 07 2003 - 08:19:43 PST
[vlog-synth] FW: DASC: draft procedures on web site
Jayaram Bhasker
Tue Nov 25 2003 - 07:17:41 PST
[vlog-synth] FW: Awards for standards activities
Jayaram Bhasker
Tue Jan 13 2004 - 08:10:10 PST
[vlog-synth] Verilog 2005
Jayaram Bhasker
Thu Jan 15 2004 - 04:04:38 PST
Re: [vlog-synth] Verilog 2005
Shalom.Bresticker@motorola.com
Fri Feb 13 2004 - 18:00:17 PST
[vlog-synth] [Fwd: Last Call for Papers - EDP 2004 - Design Process Workshop]
David Bishop
Mon Mar 08 2004 - 12:37:08 PST
[vlog-synth] This is a test message - please ignore.
Jayaram Bhasker
Sun Mar 28 2004 - 23:22:05 PST
[vlog-synth] Signed Multiplier generation
Biswas, Shiladitya
Mon Mar 29 2004 - 08:40:00 PST
Re: [vlog-synth] Signed Multiplier generation
Mark Curry
Mon Mar 29 2004 - 11:39:01 PST
Re: [vlog-synth] Signed Multiplier generation
Steven Sharp
Tue Mar 02 2004 - 10:06:41 PST
[vlog-synth] Hey, dude, it's me ^_^ :P
dbishop@server.vhdl.org
Thu May 27 2004 - 07:02:54 PDT
[vlog-synth] Dersigning FSM
Biswas, Shiladitya
Wed Apr 06 2005 - 08:25:44 PDT
[vlog-synth] FW: IEEE Std 1076.6-2004 and IEEE Std 1364.1-2002
Jayaram Bhasker
Last message date
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Wed Apr 06 2005 - 08:25:52 PDT
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: Wed Apr 06 2005 - 08:26:38 PDT
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