Subject: RE: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Tue Apr 16 2002 - 11:23:45 PDT
I noticed four bugs (these were there in the original draft as well, so were not
introduced by Cliff) which I am fixing:
1. library_text had an extra space in the middle.
2. blocking_assignment had a space instead of an underscore.
3. system_task_identifier is incorrectly marked as not supported in Annex whereas
it is marked as ignored in section 7.
4. nonblocking_assignment had a space instead of an underscore.
CLIFF:
Why are some not-supported constructs made bold blue, such as "udp_declaration",
"udp_instantiation", "real_declaration", etc? Looks like something you might have been
playing with but forgot to revert back. I think these should be regular blue,
not bold. Do you agree?
- bhasker
-----Original Message-----
From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
Sent: Friday, April 12, 2002 12:41 PM
To: vlog-synth@eda.org
Subject: Verilog Synthesis BNF - Please Review and Vote - Votes due
04/19/2002
Hi, All -
Attached are two files:
The first is a cleaned up BNF file for Verilog Synthesis. To make the
review easier, all keywords have been made bold-red, all synthesis-ignored
constructs are underlined-blue, all not-supported constructs are
strike-through-blue. All colors will be returned to black for the final
submission to the IEEE (colors are for review purposes only). Minor
corrections were made during the review and the font style has been changed
to Times font, to match the font used for the Verilog-2001 Standard (made
for easier comparison between the two Standards and it also made the BNF
fit better).
ALL BNF REVIEWS ARE DUE BY NEXT FRIDAY, APRIL 19TH.
CALL FOR VOTE - UPDATED BNF - ALSO DUE NEXT FRIDAY, APRIL 19TH.
Yesterday, I sent out an important proposal to correct the Verilog-2001
parameter port list syntax. The published Verilog-2001 BNF-syntax is wrong,
and vendors are starting to implement it incorrectly (vendors are requiring
semicolons in the Verilog-2001 parameter port list). A full description of
the problem and the proposed fix is attached (again).
I actively participate on the IEEE Verilog Standards Group, This Group
(IEEE Verilog Synthesis Interoperability Group) and the Accellera
SystemVerilog Standards Group (the SystemVerilog Standard will be handed
off to the Verilog Standards Group, chaired by Mike McNamara around June).
All three of these Standards should reflect the correct BNF syntax. I have
volunteered to coordinate comments from all three committees to arrive at
the correct BNF to fix this problem (and you thought working with just one
committee was a bureaucratic nightmare!! ;-) ;-)
Bhasker believes we should publish the existing Verilog-2001 BNF in the
Synthesis document and add a note of warning (Bhasker's comments and
reasons are shown below). I strongly disagree and believe we need to put
the correct BNF syntax in the Synthesis document as opposed to propagating
erroneous and misleading BNF. We will be issuing an errata on the
Verilog-2001 BNF. I do not want to issue errata on multiple documents as I
believe this is a recipe for propagation of buggy EDA tools.
I am asking the Verilog Synthesis committee to vote "yes" for the proposal
to add the fixed BNF to the Verilog Synthesis BNF (not currently added to
the review-BNF).
CALL FOR VOTE - UPDATED BNF PROPOSAL - DUE NEXT FRIDAY, APRIL 19TH.
Regards - Cliff
At 09:26 AM 4/12/02 -0400, Jayaram Bhasker wrote:
>Precedence: bulk
>
>Cliff:
>
>This is a very tricky issue. You really dont want two versions of verilog
>standard
>out there, one described in 1364-2001 and one in 1364.1-2002 (though I
>dont mind sales of
>1364.1 std going up just because prople want to see the latest Verilog BNF).
>
>I think a reasonable solution is to keep the 1364.1 syntax consistent with
>the 1364 syntax,
>but add a footnote in 1364.1 syntax where there is inconsistency detailing
>some words such as:
>"The Verilog BTF WG has found an errata in the 1364-2001. <then describe
>the correction>.
>The WG is most likely to accept these changes in future versions of the
>1364 language."
>
>- bhasker
>
>--
>
>J. Bhasker
>Cadence Design Systems
>7535 Windsor Drive, Suite A200, Allentown, PA 18195
>(610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
>
>
>-----Original Message-----
>From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
>Sent: Thursday, April 11, 2002 3:13 PM
>To: vlog-synth@eda.org; vlog-pp@eda.org; btf@boyd.com
>Subject: Proposed BNF Fix for Verilog-2001 Parameter Errata
>
>
>Hi, All -
>
>Proposed BNF Fix for Verilog-2001 Parameter Errata
>
>We (I) made a mistake in the Verilog-2001 BNF concerning the definition of
>the module_parameter_port_list and vendors are starting to implement these
>parameter port lists incorrectly. We need to fix this in the Verilog-2001
>Standard (issue an errata notice), but we also need to make sure that the
>errata does not propagate to the IEEE Verilog-Synthesis (1364.1) and
>SystemVerilog (Accellera) standards to compound the problem.
>
>Attached is a full description of the problem and a proposed fix.
>
>Please read and respond.
>
>Regards - Cliff Cummings
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