/bbs/pub/vlog-synth By Author
- Alain RAYNAUD
- Alain Vachoux
- Apurva Kalia
- Biswas, Shiladitya
- Cliff Cummings
- Clifford E. Cummings
- Daryl Stewart
- David Bishop
- dbishop@server.vhdl.org
- Don Hejna
- Erich Marschner
- frm145
- Gilbert Nguyen
- J. Bhasker
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02 (Wed Jan 16 2002 - 11:33:20 PST)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02 (Wed Jan 16 2002 - 08:28:40 PST)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02 (Fri Jan 11 2002 - 06:20:19 PST)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02 (Thu Jan 10 2002 - 13:52:59 PST)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02 (Tue Jan 08 2002 - 06:19:28 PST)
- FW: 1364.1 draft 1.8 (Thu Jan 03 2002 - 11:02:29 PST)
- RE: D1_7 Pragmas Proposal - Section 6 - (updated 20011206) (Tue Dec 18 2001 - 09:30:02 PST)
- RE: new attribute (* synthesis, combinational *) (Mon Dec 17 2001 - 12:23:58 PST)
- FW: Fwd: Implicit FSMs style with mutiple clocks (Fri Dec 14 2001 - 11:20:21 PST)
- RE: FSM Enhancement Goals and Thoughts (Thu Dec 13 2001 - 11:35:31 PST)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01 (Tue Dec 11 2001 - 09:56:59 PST)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01 (Mon Dec 03 2001 - 10:54:50 PST)
- Meeting Minutes: Verilog Synthesis Interoperability Working Group Meeting on Nov 2, '01 (Tue Nov 06 2001 - 11:27:28 PST)
- RE: Minor corrections to IEEE P1364.1 / D1.7 (Fri Nov 02 2001 - 06:07:26 PST)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01 (Thu Nov 01 2001 - 06:06:29 PST)
- RE: Attributes & Synthesis Pragmas (Thu Oct 25 2001 - 06:53:12 PDT)
- RE: Attributes and constant expressions (Thu Oct 25 2001 - 06:20:56 PDT)
- RE: Attributes and constant expressions (Thu Oct 25 2001 - 06:13:30 PDT)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01 (Wed Oct 24 2001 - 08:52:29 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01 (Tue Oct 23 2001 - 11:50:56 PDT)
- RE: Verilog: ROMRAM Revision 2 (Thu Oct 11 2001 - 11:48:55 PDT)
- RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01 (Mon Oct 08 2001 - 12:37:37 PDT)
- RE: Initial Blocks fail with Synopsys Tools (Mon Oct 08 2001 - 11:54:15 PDT)
- FW: (Fri Oct 05 2001 - 07:04:01 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01 (Mon Oct 01 2001 - 08:41:34 PDT)
- Re: Synopsys support for Verilog-2001 (Wed Sep 26 2001 - 11:07:50 PDT)
- Re: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01 (Tue Jun 19 2001 - 13:03:23 PDT)
- Verilog2K synthesis features (Fri Jun 15 2001 - 08:54:38 PDT)
- New updated Verilog Synthesis draft, D1.6 (Fri Jun 15 2001 - 08:41:23 PDT)
- Verilog2K synthesis features (Fri Jun 01 2001 - 11:12:47 PDT)
- Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01 (Wed May 30 2001 - 06:09:43 PDT)
- Jayaram Bhasker
- Jayaram Bhasker
- 1364.1 in ballot (Wed May 15 2002 - 13:02:53 PDT)
- RE: Draft D2.2 for ballot (Fri Apr 26 2002 - 06:44:11 PDT)
- Draft D2.2 for ballot (Thu Apr 25 2002 - 13:27:24 PDT)
- RE: section 5.6 ROM // Question (Thu Apr 25 2002 - 06:22:07 PDT)
- RE: Verilog Synthesis BNF - Please Review and Vote - Votes due 04/19/2002 (Tue Apr 16 2002 - 11:23:45 PDT)
- RE: Proposed BNF Fix for Verilog-2001 Parameter Errata (Fri Apr 12 2002 - 06:26:49 PDT)
- RE: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02 (Mon Apr 08 2002 - 06:41:14 PDT)
- RE: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02 (Thu Apr 04 2002 - 12:37:11 PST)
- Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02 (Fri Mar 29 2002 - 07:53:58 PST)
- Updated 1364.1 v2.1 draft available (Fri Mar 29 2002 - 07:47:59 PST)
- Another attribute: test_port (Wed Mar 27 2002 - 08:27:09 PST)
- RE: Assignments in the Verilog RTL Synthesizes draft (Mon Mar 25 2002 - 14:22:17 PST)
- Verilog Synthesis Interoperability WG: NO MEETING ON MARCH 22 (Mon Mar 18 2002 - 12:52:10 PST)
- Verilog Synthesis WG Meeting minutes: March 11, 2002 (Fri Mar 15 2002 - 13:47:24 PST)
- 1364.1 WG meeting at HDLCON (Wed Mar 06 2002 - 11:24:21 PST)
- 1364.1 WG meeting at HDLCON (Wed Mar 06 2002 - 07:20:47 PST)
- RE: Annex B Replacement Proposal (Mon Mar 04 2002 - 13:23:59 PST)
- Some review comments (Thu Feb 28 2002 - 12:07:27 PST)
- FW: Editorial coordination on draft 1364.1 (Tue Feb 26 2002 - 09:54:24 PST)
- RE: Verilog Synthesis draft 2.0 // Comments (Mon Feb 25 2002 - 06:32:50 PST)
- FW: Verilog Synthesis draft 2.0 (Wed Feb 13 2002 - 06:16:14 PST)
- FW: Invitation to Ballot for P1364.1 (Tue Feb 12 2002 - 08:24:12 PST)
- RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES (Fri Feb 08 2002 - 13:37:50 PST)
- RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002: MEETING MINUTES (Fri Feb 08 2002 - 11:57:19 PST)
- RE: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002 (Fri Feb 08 2002 - 06:09:20 PST)
- Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002 (Mon Feb 04 2002 - 11:13:19 PST)
- RE: (* synthesis, keep [=<optional_value>] *) (Fri Feb 01 2002 - 11:42:53 PST)
- RE: Draft 1.9 // synthesis encoding vs state_machine (Thu Jan 31 2002 - 10:19:14 PST)
- Attribute "encoding" (Tue Jan 22 2002 - 14:04:19 PST)
- Meeting minutes - Verilog Synthesis Working Group Meeting: Sept 7, 2001 (Fri Sep 14 2001 - 07:20:02 PDT)
- Conference Call Minutes, Aug 10, 2001 (Mon Sep 10 2001 - 12:40:46 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Sep 07, '01 (Thu Aug 30 2001 - 10:27:08 PDT)
- Verilog Synthesis Interoperability Working Group Meeting: Agenda for Aug 10, '01 (Mon Aug 06 2001 - 08:49:31 PDT)
- Re: constant function (Fri Jul 20 2001 - 07:36:58 PDT)
- RE: vlog 2000 feature list (Thu Jul 19 2001 - 09:19:00 PDT)
- RE: vlog 2000 feature list (Thu Jul 19 2001 - 09:11:34 PDT)
- HDLCon 2002 Call for Papers (Thu Jul 19 2001 - 08:41:24 PDT)
- fullcase/parallel case (fwd) (Wed Jul 11 2001 - 10:13:38 PDT)
- Re: Proposed styles for Inferring ROMs in Verilog (Wed Jul 11 2001 - 10:04:27 PDT)
- FDL 2001 Advance Program Announcement (Wed Jul 11 2001 - 07:57:51 PDT)
- Re: Using initialization statements for defining initial setup of registers (Tue Jul 10 2001 - 11:46:08 PDT)
- vlog 2000 feature list (Fri Jul 06 2001 - 12:57:21 PDT)
- Re: Inferring ROMs in Verilog (Fri Jul 06 2001 - 06:46:42 PDT)
- Re: Inferring RAMs in Verilog (Fri Jul 06 2001 - 06:49:49 PDT)
- Re: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01 (Thu Jul 05 2001 - 09:01:02 PDT)
- Re: SLR Balloting Feedback Request (fwd) (Mon Oct 16 2000 - 11:26:19 PDT)
- Re: problem with item 25 (Wed Sep 27 2000 - 12:59:52 PDT)
- RE: verilog 2000 feature list (Wed Sep 27 2000 - 08:51:09 PDT)
- verilog 2000 feature list (Wed Sep 27 2000 - 06:32:54 PDT)
- Here we go again ... (Tue Sep 26 2000 - 06:18:16 PDT)
- OVI/Accellera Membership Rights (Thu Jun 01 2000 - 05:01:33 PDT)
- International HDL Conference 2000 CALL FOR PAPERS (Fri Dec 10 1999 - 11:22:45 PST)
- Re: Next 1364.1 working group meeting: REMINDER!!!! (Thu May 06 1999 - 11:48:28 PDT)
- Re: Compilation pragmas (Wed Apr 28 1999 - 08:18:37 PDT)
- Next 1364.1 working group meeting (Tue Apr 27 1999 - 12:47:49 PDT)
- Draft 1.4 Verilog RTL synthesis (Tue Apr 27 1999 - 12:42:56 PDT)
- full_case, parallel_case (Fri Apr 23 1999 - 14:28:37 PDT)
- Compilation pragmas (Fri Apr 23 1999 - 14:12:08 PDT)
- Meeting Minutes: P1364.1 Verilog Synthesis WG (Fri Apr 23 1999 - 13:56:26 PDT)
- Re: Verilog Synthesis Working Group meeting: face to face (Thu Apr 01 1999 - 10:48:54 PST)
- DASC member (Wed Mar 31 1999 - 13:08:47 PST)
- Verilog Synthesis Working Group meeting: face to face (Thu Mar 25 1999 - 11:22:43 PST)
- Re: Call for DASC WG Nominations (Fri Mar 12 1999 - 13:16:02 PST)
- Review of Syntax section (Thu Mar 11 1999 - 11:28:02 PST)
- Re: Support for values x and z (Wed Mar 10 1999 - 06:14:42 PST)
- Support for values x and z (Mon Mar 08 1999 - 13:12:11 PST)
- Hierarchical names: Verilog RTL synthesis (Fri Feb 26 1999 - 06:24:16 PST)
- `celldefine issue: Verilog RTL synthesis subset (Fri Feb 26 1999 - 06:17:47 PST)
- Re: Section 5.3 Modeling level-sensitive storage devices (Wed Feb 24 1999 - 13:37:52 PST)
- Meeting Minutes: 1364.1 Verilog Synthesis Working Group Meeting (Wed Feb 24 1999 - 13:00:54 PST)
- Re: 1364.1 Verilog Synthesis Working Group Meeting: REMINDER (Fri Feb 19 1999 - 13:25:30 PST)
- 1364.1 Verilog Synthesis Working Group Meeting (Wed Feb 10 1999 - 09:09:02 PST)
- Jayaram_Bhasker
- Jbhasker7@aol.com
- jbhasker@lucent.com
- Jenjen Tiao
- Jenjen_Tiao
- Jim Hudson
- John Michael Williams
- Joseph P. Wetstein
- kcoffman@sos.net
- Ken Coffman
- Krishna Garlapati
- lech@ics.ele.tue.nl
- M Ciletti
- Mark Curry
- mcurry@ti.com
- Michael McNamara
- Muzaffer Kal
- Nikitas Assimakopoulos
- nunez@cma.ulpgc.es
- Pat Bryant
- Paul Graham
- Paul J. Menchini
- Praveen Tiwari
- Sampath Prithivadhi Bayankaram
- Sashi Obilisetty
- Shalom Bresticker
- Shalom Bresticker (r50386)
- Shalom.Bresticker@motorola.com
- Stefen Boyd
- Steve Golson
- Steven Schulz
- Steven Sharp
- tiao@agere.com
- Tom Fitzpatrick
- Tommy Kelly
- VhdlCohen@aol.com
- villar@teisa.unican.es
- Vinaya Singh
- Yatin Trivedi
- Last message date: Wed Apr 06 2005 - 08:25:52 PDT
- Archived on: Wed Apr 06 2005 - 08:26:39 PDT