Verilog Synthesis Interoperability Working Group Meeting: Agenda for Sep 07, '01

Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Sep 07, '01
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Thu Aug 30 2001 - 10:27:08 PDT

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The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, SEPTEMBER 07 from 12:00pm to 1:30pm
EASTERN STANDARD TIME.
    
Call:
 CALL DATE: SEP-07-2001 (Friday)
 CALL TIME: 12:00 PM EASTERN TIME
 DURATION: 1 hr 30 min
 USA Toll Free Number: 877-716-4285
 USA Toll Number: +1-712-271-3621
 PASSCODE: 12550
    
Agenda:
    
1. To discuss the synthesizability of the new features
   of Verilog-2000. Following to report on their assigned items:
    
     - StephenBoyd
     - CliffCummings
     - JenjenTiao
     - MuzaffarKal
     - JoeWetstein : attribute format
      
     If you cannot make it to the meeting, please post your comments on the
     reflector prior to the meeting. I would like to close on the
     2000 features soon.

2. To continue to discuss RAM and ROM modeling - BenCohen.

3. To start reviewing the latest draft D1.7 (change bars highlight the diff from
   1.6).
    
Future telecon dates: Oct 5, Nov 2.

Regards,
    
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
 Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
 Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth

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