Subject: Navabi use of buried initial statement
From: Ken Coffman (kcoffman@sos.net)
Date: Sat Sep 01 2001 - 10:58:27 PDT
Hi folks. During the last 1364.1 conference call, I said I'd send a copy of
some Navabi code (from Verilog Digital System Design, McGraw Hill, 1999)
which includes a rather nasty use of a buried initial statement. An example
is on page 441 (State Machine Synthesis), the example below is similar and
is taken from Navabi's CD-ROM. I'm including the file as an attachment and
as a listing below.
Sorry for the delay in getting this out, things have been crazy around here.
- Best.
`timescale 1ns/1ns
`define reset 2'd0
`define got1 2'd1
`define got11 2'd2
`define got110 2'd3
module moore_110_detector (x, clk, z);
input x, clk;
output z;
// reg z;
wire x, clk;
reg [1:0] current, next;
//
initial current = `reset;
always @(posedge clk) current = next;
always @(current)
begin
case(current)
`reset :
if (x == 1) next = `got1;
else next = `reset;
`got1 :
if (x == 1) next = `got11;
else next = `reset;
`got11 :
if (x == 1) next = `got11;
else next = `got110;
`got110 :
if (x == 1) next = `got1;
else next = `reset;
default :
next = `reset;
endcase
end
// always @(current)
// if (current == `got110) z = 1; else z = 0;
assign z = (next == `got110) ? 1 : 0;
endmodule
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