Meeting minutes - Verilog Synthesis Working Group Meeting: Sept 7, 2001

Subject: Meeting minutes - Verilog Synthesis Working Group Meeting: Sept 7, 2001
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Fri Sep 14 2001 - 07:20:02 PDT

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Meeting minutes
Verilog Synthesis Interoperability Working Group
Teleconference, Sept 9, 2001

Attendees:
Cliff Cummings
Paul Graham
J. Bhasker
Ben Cohen

1. Ben brought up the issue of lack of structures(records) in Verilog. He
suggested that a workaround for this was to treat modules as records and
thence support hierarchical names for synthesis. This issue needs further
discussion.

2. The meeting was called off early as most of the participants were not
prepared with their agenda items.

Next WG meeting is on Oct 5, 2001.

- bhasker

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