Subject: Re: Attribute "encoding"
From: VhdlCohen@aol.com
Date: Tue Jan 22 2002 - 15:47:11 PST
In a message dated 1/22/02 2:24:44 PM Pacific Standard Time,
jbhasker@cadence.com writes:
> Still working on adding the new attributes to the draft. However, am not yet
> clear
> how the "encoding" attribute works.
>
> The way it is defined currently, it applies to a reg, such as:
>
> (* synthesis, encoding = "onehot" *) reg [3:0] counter;
>
> So what does this mean? Does it mean that counter can only have onehot
> values?
> What if user assigns a value "1100" to it explicitly? What if user says
> "counter = counter + 1"? This attribute can further cause
> potential mismatches in simulation.
>
> I believe that this attribute applies only to state registers when
> describing a design using
> a VERY SPECIFIC FSM style and therefore does not apply to the standard that
> we are
> currently working on.
>
From Synplify help file:
" syn_encoding is a Directive that sets the encoding style for a state
machine, overriding the default style. When the FSM compiler is enabled, the
software automatically chooses an FSM encoding style during the compile
phase, based on the number of states.
Verilog Syntax and Examples
object /* synthesis syn_encoding = "value" */ ;
where object can be register definition signals that hold the state values of
state machines and value can be: onehot, gray, sequential, safe, default.
In this example, the default encoding style for current_state is being
overridden by the gray encoding style.
module prep3 (CLK, RST, IN, OUT);
input CLK, RST;
input [7:0] IN;
output [7:0] OUT;
reg [7:0] OUT;
reg [7:0] current_state /* synthesis syn_encoding="onehot" */;
/* Other coding */
// Thus, in the code I could have
current_state <= next_state; // in a clocked process
in another always statement
case (current_state)
X: next_state = 1;
Y: next_state = current_state + 2;
...
Z : next_state = 7;
If this FSM has 8 states, the synthesizer will be a one-hot with 8 registers.
If encoding is GRAY or SEQUENTIAL, then you'll have a 3-bit implementation.
Thus, you can add a "1" to next_state because synthesizer counts the number
of states, and then picks an encoding scheme, as directed by the directive.
At least that's my understanding of it.
Ben
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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