Subject: Draft 1.9 // synthesis encoding vs state_machine
From: VhdlCohen@aol.com
Date: Wed Jan 30 2002 - 15:45:11 PST
(* synthesis, keep [=<optional_value>] *)
The (* synthesis, encoding=1*) vs (* synthesis, state_machine =
"some_type"*) were not in the draft. We had a pending discussion on that
topic at our last telecon. I think that both encoding and state_machine
are both needed.
The synthesis, state_machine
1. Enables/Disables state-machine extraction on individual state registers in
the design.
2. Identifies registers as FSM, if tool cannot automatically do it.
the synthesis encoding
1. Defines an encoding style for the state machine.
2. Potential different values for this attribute include:
Sequential
Onehot
Gray
other (user defined)
To override the default encoding styles, one can use the encoding directive
with the state_machine directive.
I vote that we adopt them both.
Ben
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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