Subject: RE: Draft 1.9 // synthesis encoding vs state_machine
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Thu Jan 31 2002 - 10:19:14 PST
Ben:
These two attributes relate to FSM extraction. So before we introduce these two attributes, we need to
define what FSM extraction is. So here is what I propose:
----------------------
FSM extraction is the process of extracting a state transition table
with tuples of the form "current_state next_state actions" from an RTL
model. In such a case, it may be necessary to guide the synthesis tool in
identifying the state register explicitly and to provide a mechanism to override the default encodings if necessary.
If a synthesis tool supports FSM extraction, then the following attribute shall also be supported
( i dont see the need for two attributes: one seems to be sufficient):
(* synthesis, fsm_state=<encoding_scheme> *) -- applies to a reg.
The attribute when applied to a reg identifies the reg as the state vector.
The encoding_scheme is optional. If no encoding is specified, the default encoding as specified in
the model is used. The value of encoding_scheme is not defined by this standard.
Note: Use of encoding scheme may cause simulation mismatches.
Examples:
(* synthesis, fsm_state *) reg [4:0] next_state; // Default encoding is used and "next_state" is the state vector.
(* synthesis, fsm_state="onehot" *) reg [7:0] rst_state; // "onehot" encoding is used and "rst_state" is the state vector.
-----------------------
Comments?
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: VhdlCohen@aol.com [mailto:VhdlCohen@aol.com] Sent: Wednesday, January 30, 2002 6:45 PM To: vlog-synth@eda.org Subject: Draft 1.9 // synthesis encoding vs state_machine
(* synthesis, keep [=<optional_value>] *) The (* synthesis, encoding=1*) vs (* synthesis, state_machine = "some_type"*) were not in the draft. We had a pending discussion on that topic at our last telecon. I think that both encoding and state_machine are both needed.
The synthesis, state_machine 1. Enables/Disables state-machine extraction on individual state registers in the design. 2. Identifies registers as FSM, if tool cannot automatically do it. the synthesis encoding 1. Defines an encoding style for the state machine. 2. Potential different values for this attribute include: Sequential Onehot Gray other (user defined)
To override the default encoding styles, one can use the encoding directive with the state_machine directive. I vote that we adopt them both. Ben
---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www. <http://www.vhdlcohen.com/> vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------
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