FW: 1364.1 draft 1.8

Subject: FW: 1364.1 draft 1.8
From: J. Bhasker (jbhasker@cadence.com)
Date: Thu Jan 03 2002 - 11:02:29 PST

Next message: J. Bhasker: "Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02"
Previous message: J. Bhasker: "RE: D1_7 Pragmas Proposal - Section 6 - (updated 20011206)"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Thanks to David Bishop for posting the lastest draft. David continues to do
an excellent job
as our WG site administrator.

Draft 1.8 of the Verilog Synthesis standard is now online at
http://www.eda.org/vlog-synth.
This version of draft includes RAM/ROM modeling (from Ben Cohen's proposal)
and
an updated section on Pragmas (from Cliff Cumming's proposal).

Please review and be prepared to provide feedback on Jan 11 WG meeting.

- bhasker

J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com

-----Original Message----- From: David W. Bishop [mailto:dbishop@vhdl.org] Sent: Thursday, January 03, 2002 1:58 PM To: Paul J. Menchini Cc: J. Bhasker Subject: Re: 1364.1 draft 1.8

New spec is loaded on the "draft documentation" page.

-- David W. Bishop dbishop@vhdl.org All standard disclaimers apply.

Next message: J. Bhasker: "Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02"
Previous message: J. Bhasker: "RE: D1_7 Pragmas Proposal - Section 6 - (updated 20011206)"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Thu Jan 03 2002 - 11:34:45 PST