Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Wed Dec 12 2001 - 22:53:21 PST
But Synopsys Design Compiler does not support it, to the best of my knowledge.
Shalom
VhdlCohen@aol.com wrote:
> By the way, Synplify also synthesizes that code. Attached is a PDF of the code and result. And that brings an interesting
> question: Do we want to include the support of Implicit FSMs style with mutiple clocks? I read Cliff's answer, and he has good
> points, but the tools seem to support this style. In other words, if vendors support the multiple clocks in a block, do we really
> want to say "NO, we won't let you do that". I thought our job is not necessarily to teach good style, but rather define
> templates and attributes for use in interroperability. From our spec "1.1 Scope
> This standard defines a set of modeling rules for writing Verilog HDL descriptions". These are not guidelines on how to do
> design.
> Comments?
> Ben Cohen
-- Shalom Bresticker Shalom.Bresticker@motorola.com Principal Staff Engineer Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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