Subject: Re: Minor corrections to IEEE P1364.1 / D1.7
From: Joseph P. Wetstein (jpw@cbis.ece.drexel.edu)
Date: Thu Nov 01 2001 - 11:17:46 PST
Any chance on seeing this document before tomorrow?
> 2 suggested corrections:
>
> 1.1 Scope
> This standard defines a set of modeling rules for writing Verilog HDL
> descriptions for synthesis. Adherence to these rules guarantees the
> interoperability of Verilog HDL descriptions between register-transfer level
> synthesis tools that comply to this standard.
>
>
>
> Section 6
> Pragmas
> A pragma is a generic term used to define a construct with no predefined
> language semantics that influences how a synthesis tool shall should
> synthesize Verilog HDL code into a circuit.
> A synthesis tool may ignore the pragma if the constraints defined by the
> pragma cannot be met because of technology limitations (e.g., no ROM
> primitive), or speed or area constraints. Pragmas are guidelines.
>
> ----------------------------------------------------------------------------
> Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
> <A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
> Author of following textbooks:
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ------------------------------------------------------------------------------
>
-- Joseph P. Wetstein, P.E. j.wetstein@ieee.org (707) 202-0600 fax PP/ASEL & KA3VJY [Tech+]
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