Subject: Re: Minor corrections to IEEE P1364.1 / D1.7
From: VhdlCohen@aol.com
Date: Thu Nov 01 2001 - 11:35:29 PST
In a message dated 11/1/01 11:18:07 AM Pacific Standard Time,
jpw@coe.drexel.edu writes:
> Any chance on seeing this document before tomorrow?
>
>
> Attached is my correction (same as the text in my message).
The IEEE P1364.1 / D1.7 Draft Standard for VerilogŪ Register
Transfer Level Synthesis is at
http://www.eda.org/vlog-synth/drafts.html
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
This archive was generated by hypermail 2b28 : Thu Nov 01 2001 - 11:41:27 PST