Subject: ROM definitions from within tasks and functions
From: VhdlCohen@aol.com
Date: Thu Nov 01 2001 - 12:19:54 PST
My previous ROM spec defined a method to specify a ROM using three styles:
1. Case statement of address with assignment to vector output (section
5.6.1). The case statement shall be within an always block.
2. Initial statement of a memory array with values defined in Verilog code
(section 5.6.2).
3. Initial statement with memory initialized with $readmemb or $readmemh.
ROM data shall be in a text file (section 5.6.3).
Tomorrow, I would like you guys to think about how ROMs can be defined from
within functions and tasks, without defining initial statements outside the
scope of the functions and tasks.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
This archive was generated by hypermail 2b28 : Thu Nov 01 2001 - 12:25:40 PST