Subject: Re: ROM definitions from within tasks and functions
From: VhdlCohen@aol.com
Date: Thu Nov 01 2001 - 14:42:22 PST
The ROMs previously discussed were standalone definitions. My point is to
how they could be defined from within functions and tasks that could be
complex, and make use of internal ROMS. In VHDL, I can define constants of
type memory that are local to a subprogram. The constant is initialized at
declaration.
Ben
In a message dated 11/1/01 12:25:08 PM Pacific Standard Time,
jpw@coe.drexel.edu writes:
> Doesn't allowing it from a function only make the most sense? That is
> basically how it is used...
>
> > My previous ROM spec defined a method to specify a ROM using three
> styles:
> > 1. Case statement of address with assignment to vector output (section
> > 5.6.1). The case statement shall be within an always block.
> > 2. Initial statement of a memory array with values defined in Verilog
> code
> > (section 5.6.2).
> > 3. Initial statement with memory initialized with $readmemb or
> $readmemh.
> > ROM data shall be in a text file (section 5.6.3).
> >
> > Tomorrow, I would like you guys to think about how ROMs can be defined
> from
> > within functions and tasks, without defining initial statements outside
> the
> > scope of the functions and tasks.
>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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