Subject: 1364.1 passes second recirculation ballot
From: Jayaram Bhasker (JBhasker@esilicon.com)
Date: Mon Sep 30 2002 - 06:10:25 PDT
Dear WG member:
It takes me great pleasure to inform you that 1364.1 passed its second
recirculation ballot with a resounding success.
My thanks to all WG members for making this a true and useful standard.
IEEE Std 1364.1 Verilog RTL Synthesis is almost a standard - only need final
approval from the IEEE.
- bhasker
------
J. Bhasker
Chair, Verilog Synthesis Interoperability Working Group
http://www.eda.org/vlog-synth <http://www.eda.org/vlog-synth>
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
_____
<http://promos.hotbar.com/promos/promodll.dll?RunPromo&El=hotbar%5felement%3
bst%3b&SG=&RAND=1>
This archive was generated by hypermail 2b28 : Mon Sep 30 2002 - 06:22:15 PDT