Subject: RE: Annex B Replacement Proposal
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Mon Mar 04 2002 - 13:23:59 PST
I like Cliff's proposal. Its looks good - thank you, Cliff.
Couple of nits (which I will correct in the draft):
- Should mismatch be with an hyphen as in mis-match?
B.1: "This document ..." to "This annex ...".
title for full_case: should be "(* synthesis ...."
2nd page, first para: period needed. Add comment to example:
// en is the enable signal.
title for parallel_case: should be "(* synthesis ..."
3rd page, 4th para from bottom: should be "there are no simulation-functional ..."
3rd page, last example: I think the inputs and output are vectors, since the
text talks about bitwise-or and bitwise-and; also operators are bit operators.
Maybe I will add size of [3:0] to all.
4th page, 2nd para: only one period.
4th page, 3rd para: Change sentence in beginning of para
to "The @* combinational sensitivity list
feature can be used to reduce redundant typing ...".
4th page: Change to and'ed and or'ed (in 2 places).
Last para in "Functions": not sure if this para is really needed since it applies to
all topics in this annex.
In "Making X assignments": change to "sel signal". Change "x-output" to "x value".
In "Assig.. var..decl...", modify first sentence to "A variable may be initialized
it its declaration. Making assignments ..."
- bhasker
-----Original Message-----
From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
Sent: Friday, March 01, 2002 2:53 PM
To: vlog-synth@eda.org
Subject: Annex B Replacement Proposal
Hi, All -
Per my action item, attached is a PDF proposal for a replacement of Annex B
in the Verilog Synthesis draft document.
Bhasker to add the appropriate section heading numbers and bolding of
appropriate words in the text.
Regards - Cliff
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