RE: Verilog RTL Synthesis ballot passes!

Subject: RE: Verilog RTL Synthesis ballot passes!
From: Michael McNamara (mac@verisity.com)
Date: Wed Jun 26 2002 - 09:16:33 PDT

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Jbhasker7@aol.com writes:
> Dear WG members:
>
> I am very pleased to report that the 1364.1 Verilog RTL Synthesis standard
> ballot
> has passed with a resounding 86% affirmative. It has passed its biggest
> challenge and is expected to officially become an IEEE standard soon.
>
> My sincere thanks and appreciation to all the WG members who have contributed
>
> to the development of this standard.
>
> Regards,
>
> - J. Bhasker, jbhasker@ieee.org, 610.248.8454
> Chair, IEEE Verilog Synthesis Interoperability Working Group
> vlog-synth@eda.org, http://www.eda.org/vlog-synth
>

Wonderful news!

Congratulations to the team.

Michael McNamara
IEEE 1364 WG Chair

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