Subject: Re: Verilog RTL Synthesis ballot passes!
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed Jun 26 2002 - 10:08:52 PDT
Bhasker -
Do we need to have another call to discuss replies to the votes?
Seems like the committee needs to respond and then everyone gets one more
chance to change their vote (in either direction).
Regards - Cliff
At 11:12 AM 6/26/02 -0400, Jbhasker7@aol.com wrote:
>Dear WG members:
>
>I am very pleased to report that the 1364.1 Verilog RTL Synthesis standard
>ballot
>has passed with a resounding 86% affirmative. It has passed its biggest
>challenge and is expected to officially become an IEEE standard soon.
>
>My sincere thanks and appreciation to all the WG members who have contributed
>
>to the development of this standard.
>
>Regards,
>
>- J. Bhasker, jbhasker@ieee.org, 610.248.8454
> Chair, IEEE Verilog Synthesis Interoperability Working Group
> vlog-synth@eda.org, http://www.eda.org/vlog-synth
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
This archive was generated by hypermail 2b28 : Wed Jun 26 2002 - 10:17:47 PDT