Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
From: J. Bhasker (jbhasker@cadence.com)
Date: Fri Jan 11 2002 - 06:20:19 PST
Paul:
Architecture attribute: I presume it applies only to operators.
merge_boundary: not clear on this. Is it that if the attribute is set, the
hierarchy of the operator
logic is maintained?
sync_blocks, async_blocks: what are a, b, c?
what are s1, s2, s3? Can you explain via a small example if possible?
- bhasker
-----Original Message-----
From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On
Behalf Of Paul Graham
Sent: Thursday, January 10, 2002 11:21 PM
To: jbhasker
Cc: vlog-synth@eda.org
Subject: Re: Verilog Synthesis Interoperability Working Group Meeting:
Agenda for Jan 11, '02
Bhasker,
I'm afraid I'll have to miss tomorrow's verilog synthesis meeting.
In case you need it, I'm sending the list of Ambit synthesis pragmas,
along with suggested attribute equivalents.
Paul
-- begin --
Ambit-specific attributes:
// specify an architecture: cla, ripple, etc.
architecture = cla
(* synthesis, architecture = "cla" *)
// sets boundary on operator merging
merge_boundary
(* synthesis, merge_boundary *)
// specify set/reset control for registers inferred from named blocks
set_reset [a]synchronous blocks = "a,b,c"
(* synthesis sync_blocks = "a,b,c" *)
(* synthesis async_blocks = "a,b,c" *)
// specify signals to connect to [a]synchronous set/reset pins
set_reset [a]synchronous signals = "s1,s2,s3"
(* synthesis sync_signals = "s1,s2,s3" *)
(* synthesis [a]sync_signals = "s1,s2,s3" *)
// specify signals in block "a" only to connect to [a]synchronous
// set/reset pins
// I'm not sure how to specify this in attribute format
set_reset [a]synchronous block(a) = "s1,s2,s3"
-- end --
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