Subject: Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
From: Paul Graham (pgraham@cadence.com)
Date: Fri Jan 11 2002 - 07:31:03 PST
Bhasker,
Sorry, I should have provided some examples.
> Architecture attribute: I presume it applies only to operators.
It applies to operators. For instance:
assign x = a + /* ambit synthesis architecture = ripple */ b;
implies a ripple adder. In attribute syntax:
assign x = a (* synthesis, architecture = "ripple" *) + b;
> merge_boundary: not clear on this. Is it that if the attribute is set, the
> hierarchy of the operator
> logic is maintained?
More like the operator is not merged with any downstream operators in the
datapath implementation. I'm not sure why you would want to use this
attribute, but I suppose the datapath guys have their reasons.
For the [a]sync block and signal directives, the idea is to hint that a
given signal is a synch/async set or reset pin, or that the register implied
by a given block uses sync/asynch set/reset logic, or that a signal in a
given block is a sync/asynch set/reset pin. What it comes down to is
specifying the name of a signal or a block or both. Since an attribute
instance may have only a single constant expression, it's a bit awkward to
specify both block name and a signal name in a single attribute instance.
Here are some examples:
1. Here, blk_1 is hinted to have a synchronous set and reset. An attribute
equivalent might be
(* synthesis, set_reset_sync_block = "blk_1" *)
// ambit synthesis set_reset synchronous blocks = "blk_1"
always @(posedge clk) begin: blk_1
if (set)
out1 = 1 ;
else if (rst)
out1 = 0 ;
else out1 = in ;
end
2. Here, signals set1 and rst1 are hinted to be synchronous set and reset
pins:
(* synthesis, set_reset_sync_signal = "set1" *)
(* synthesis, set_reset_sync_signal = "rst1" *)
//ambit synthesis set_reset synchronous signals="set1, rst1"
always @(posedge clk) begin
if (set1)
out1 = 1 ;
else if (rst1)
out1 = 0 ;
else out1 = in ;
end
3. Here, signal rst in block blk_1 is hinted to be a synchronous reset.
(* synthesis set_reset_sync_block_signal = "blk_1, rst" *)
/* ambit synthesis set_reset synchronous block(blk_1) = "rst" */
always @(posedge clk) begin:blk_1
if (rst)
out1 = 0;
else out1 = in ;
end
I admit that these three pragmas look pretty ugly when transformed into
attributes!
Paul
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