Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
From: Gilbert Nguyen (nguyen@ibiquity.com)
Date: Fri Jan 11 2002 - 08:51:30 PST
Paul,
If one uses this attribute, will the synthesis tool always implement
a + b as a ripple adder? Or the first implementation is a ripple adder
and it can change to a carry look ahead adder if the speed constraint
increase?
Thanks,
Gilbert Nguyen
> Architecture attribute: I presume it applies only to operators.
It applies to operators. For instance:
assign x = a + /* ambit synthesis architecture = ripple */ b;
implies a ripple adder. In attribute syntax:
assign x = a (* synthesis, architecture = "ripple" *) + b;
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