RE: (* synthesis, keep [=<optional_value>] *)


Subject: RE: (* synthesis, keep [=] *)
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Fri Feb 01 2002 - 11:42:53 PST


Based on the trail of emails on this topic, here is what I propose to change in draft 1.9:
 
1. Delete the ff_preserve attribute and use the "keep" attribute for flip-flops also (Good idea, Ben).
 
2. Add comment to the effect that "... shall be preserved (not deleted nor replicated) ...".
 
- bhasker
 

--

J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com

-----Original Message----- From: VhdlCohen@aol.com [mailto:VhdlCohen@aol.com] Sent: Wednesday, January 30, 2002 6:45 PM To: vlog-synth@eda.org Subject: (* synthesis, keep [=<optional_value>] *)

There are several objects that a user may wish to "keep" during synthesis. 1. Wire: This assures that (1) a wire will be kept during synthesis and (2) that no optimizations will cross the wire. This is for nets and combinational logic. Example: wire [7:0] out_a (* synthesis, keep *);

2. sequential element: This assures that no optimizations cross a sequential element. It is usually used break unwanted optimizations which go through sequential elements. Example: reg [7:0] b (* synthesis, keep *);

3. instantiated instances: This is used to assure that instantiated instances are not optimized away. This will prevent the optimizations from removing an unconnected instance. my_design my_design1 (out1, in1, clk_in)(* synthesis, keep= 1*); // keep my_design my_design2 (out, in, clk_in)(* synthesis, keep= 0*); // may optimize out

After thinking about it, I think that we could just restrain this attribute to just one. SOme vendors provide different attribute names for each class of object. We'll discuss this at out meeting, but comments are always welcomed. ---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www. <http://www.vhdlcohen.com/> vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------



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