Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
From: J. Bhasker (jbhasker@cadence.com)
Date: Wed Jan 16 2002 - 08:28:40 PST
Meeting Minutes: Teleconference Jan 11, 2002.
===============
Attendees:
Joe Wetstein
Ben Cohen
Stefan Boyd
Jenjen Tiao
Cliff Cummings
J. Bhasker
1. Discussed attributes. Here is the list of additional
attributes that were agreed upon (i have attached a file).
(This list may be refined later based on Cliff's proposals on additional
pragmas
that are expected by our next meeting date in Feb).
(i did change some of these after having thought some more - some names
are changed and
noprune is merged with keep).
2. Reviewed draft 1.8.
Jenjen made some comments and observation on the use of word "attribute"
"pragma" and "directive".
Jenjen to post specific items noted and Bhasker to correct draft.
Bhasker made comment about "Annex B" - it is sort of hanging in there,
rather incomplete.
Cliff had contributed the earlier material and he agreed to contribute
more material by the
March meeting date.
3. The draft will stay in review mode until end of March. All members are
requested to review and
post comments. This is the last chance to review before we go to ballot.
4. Plan to go to ballot May/June timeframe - thus we need to start the
balloting process,
the first step of which is to form the balloting pool. Bhasker to
initiate this.
5. Cliff suggested that there may be a time slot available at the HDLCON
conference to provide
an update of the 1364.1 WG status. WOULD ANYONE BE INTERESTED IN
PROVIDING THIS UPDATE? If so,
please contact Cliff (cliffc@sunburst-design.com).
6. Next meeting is on Feb 8. Will have face-to-face meeting at HDLCON in
March (date and time yet
to be decided).
7. Here is what I think the future roadmap is (we did not discuss this at
the meeting):
a. Bhasker to start formation of balloting pool.
b. Draft to be in review mode until end of March.
c. Cliff to provide feedback on any additional pragmas - Feb 8.
d. Cliff to provide feedback on Annex B - March 11/12.
e. Prepare final draft for ballot - April.
f. Go ballot - May/June.
g. Ballot resolutions - July to Sept.
h. If no recirculation required, to submit as standard in Oct 2002.
----------------------
- bhasker
-----Original Message-----
From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On
Behalf Of J. Bhasker
Sent: Tuesday, January 08, 2002 9:19 AM
To: vlog-synth@eda.org
Subject: Verilog Synthesis Interoperability Working Group Meeting:
Agenda for Jan 11, '02
The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, JANUARY 11 from 12:00pm to
1:30pm EASTERN STANDARD TIME.
Call:
USA Toll Free Number: 888-469-0503
USA Toll Number: +1-312-470-7002
PASSCODE: 57607
LEADER: Mr Jayaram Bhasker
Agenda:
1. To discuss new synthesis attributes as per action items of last meeting.
(BenC, PaulG and CliffC).
2. TO ALL: please review draft 1.8 and be prepared to present any comments.
Future telecon dates: Feb 8, 2002.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
This archive was generated by hypermail 2b28 : Wed Jan 16 2002 - 10:14:32 PST