Hierarchical names: Verilog RTL synthesis

• Messages sorted by: [ date ][ thread ][ subject ][ author ]
• Next message: Alain RAYNAUD: "Re: Hierarchical names: Verilog RTL synthesis"
• Previous message: Jayaram Bhasker: "`celldefine issue: Verilog RTL synthesis subset"
• Next in thread: Apurva Kalia: "Re: Hierarchical names: Verilog RTL synthesis"

Should hierarchical names be supported?

Here is an example.

module TOP;

COMP c (a, b, d);

always @(a)
c.m = d; <<-- c.m is a hierarchical name.
endmodule

module BOT(q);
input [0:2] q;
wire [0:2] m;

assign m = q;
endmodule

Please send in your feedback (vlog-synth@eda.org) by Mar 6.

- bhasker

• Next message: Alain RAYNAUD: "Re: Hierarchical names: Verilog RTL synthesis"
• Previous message: Jayaram Bhasker: "`celldefine issue: Verilog RTL synthesis subset"
• Next in thread: Apurva Kalia: "Re: Hierarchical names: Verilog RTL synthesis"