Re: Hierarchical names: Verilog RTL synthesis

Apurva Kalia (apurva@Cadence.COM)
Wed, 3 Mar 1999 19:24:45 +0531 (IST)

I have come across user designs that make heavy use of HRs.
As someone mentione don this alias, these are viewed as jumper
wires during the initial phases of design. I propose that HRs
should be supported in this standard.

Apurva

> From owner-vlog-synth@eda.org Fri Feb 26 19:59 IST 1999
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> Date: Fri, 26 Feb 1999 09:24:16 -0500 (EST)
> From: Jayaram Bhasker <jbhasker>
> To: vlog-synth@eda.org
> Subject: Hierarchical names: Verilog RTL synthesis
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> Sender: owner-vlog-synth@eda.org
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> Here is another issue on which we need your feedback.
>
> Should hierarchical names be supported?
>
> Here is an example.
>
> module TOP;
>
> COMP c (a, b, d);
>
> always @(a)
> c.m = d; <<-- c.m is a hierarchical name.
> endmodule
>
> module BOT(q);
> input [0:2] q;
> wire [0:2] m;
>
> assign m = q;
> endmodule
>
> Please send in your feedback (vlog-synth@eda.org) by Mar 6.
>
> - bhasker
>