Re: Hierarchical names: Verilog RTL synthesis

Alain RAYNAUD (alain_raynaud@mentorg.com)
Fri, 26 Feb 1999 15:31:19 +0100

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We have done some careful analysis here about hierarchical names... In short,
the conclusion is that if you want incremental synthesis (very fashionable now
that people synthesize million gate designs), you can't have hierarchical
names.

Our conclusion was that fast incremental synthesis is more important than
supporting hierarchical names. Customers don't use them in RTL code anyway (of
course! it's not supported). They do use it in testbenches though.

Now I will understand if everyone else prefers to support them. Just be aware
that they break all kinds of algorithms and the semantics is ill defined
(IMHO). But it's cute.

Alain.

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