Regards,
Apurva
> From owner-vlog-synth@eda.org Fri Apr 16 00:57 IST 1999
> X-Authentication-Warning: server.eda.org: majordom set sender to owner-vlog-synth@eda.org using -f
> Date: Thu, 15 Apr 1999 20:14:38 +0100
> From: Paul Likoudis <likoudis@vvl.co.uk>
> Organization: VLSI Vision Ltd.
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> To: vlog-synth@eda.org
> Subject: Modelling of level sensitive devices
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>
> Dear Posted,
>
> We have been faced with a serious synthesis issue, which was resolved by
> referring
> to the Verilog RTL Synthesis Standard, but what, with all respect, I
> think the resolution
> is not fair.
>
> Cadence's Ambit synthesis failed to recognize a latch described as:
>
> wire q = e ? d : q; // where e: enabling signal and d: data to be stored
> in q
>
> As this construct is not included in "5.3 Modelling level sensitive
> storage devices"
> it seems that the synthesizer was right.
>
> My question is: Why is the above description not accepted as one for a
> latch?
>
> Should the IEEE P1364.1/D1.3 Standard include this model or its there a
> good reason
> for not doing so? Does the Standard, simply describe the common ground
> between tools
> of major players (I never had this problem with COMPASS AsicSyn) or is
> it defining
> the acceptance of Verilog RTL, that tool manufacturers should comply to?
>
> I'm hoping this is of interest to the audience, please, accept my
> apologies if not.
>
> Sincerely,
>
> Paul Likoudis
>
> PS: I have read the discussion
> http://www.eda.org/vlog-synth/hm/0089.html, but I don't
> think my point contributes to this discussion. Even if the <= / =
> argument is resolved,
> especially if Shalom Bresticker 's suggestion is followed, I believe my
> question would
> still be valid.
>
> --
> Paul Likoudis Aviation House, tel# +44 (0) 131 539 8618
> Senior Design Engineer 31 Pinkhill, EH12 7BF fax# +44 (0) 131 539 7141
> VLSI Vision Ltd. Edinburgh, U.K. mailto:likoudis@vvl.co.uk
> -------------- A company of the STMicroelectronics Group ---------------
>
>
>
>