Attached are the meeting minutes for the P1364.1 Verilog Synthesis WG meeting
held during HDLCON.
Thanks to Patrick Bryant for taking the minutes.
- bhasker
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Meeting Minutes for RTL Synthesizable
Sub-set for Verilog (1364)
Date: 6 April, 1999
Location: San Jose, CA
Attendance:
Doug Smith Veribest
Patrick Bryant Mentor Graphics Corp
Don Hejna C2DA
J. Bhasker Cadence Design (Chair)
Andres Nordstrom Nortel
Cliff Cummings Sunburst
A) General Information:
1) Location of Verilog Standard Efforts are located
and the IEEE 1364 Home page, URL is
http://www.ovi.org/ieee-1364/Welcome.html
2) Goal of tonights meeting is to review Syntax
efforts by Don Hejna. The intent was to look
at the BNF for the full language, and remove
those constructs that are not part of the
RTL Synthesizable Subset.
B) Action Items From the Meeting
1) Don Hejna is to post the Disable Block Discussion
on the reflector for 1364.
2) All are to review any of the discussions passed along
on the reflector that are relevant to this task force.
C) Issues that were Discussed
1) Implicit FSM
Discussion was if we should support. It was
determined from the Semantic Group (Task Force?)
that this should NOT be supported. Did not
overrule.
2) Limits on level of recursion.
It was determined that the levels of recursion
had to be "fixed", much like the limits of
a loop.
3) Disabling Blocks
Decided to disable only blocks that are in
the current scope. It is assumed that
"Actions at a Distance" are NOT supported, so
cannot disable a block outside the current scoping
rules.
4) Cross Referencing Variables
At the close of the discussion, it is proposed
"User variables outside the function/task, but
inside the enclosed module, shall be supported."
5) Wired-AND/OR
Keep as is in current proposal for subset.
6) UDPs:
Will NOT be supported.
7) Pragmas for controlling Synthesis
There was a LOT of discussion around this subject.
The current proposal has pragmas in comments, and
the current subset defines pragmas for turning
synthesis ON/OFF, and Parallel and Full Case. There
are potentially many other directives, depending
upon the tool. The current suggestion is to have
the pragma for controlling Synthesis be placed in
a comment string, with the keyword "rtl_synthesis"
preceding the directive, .e.g.
// rtl_synthesis <directive>
There is a desire to move the standard in the future
so that comments need not be parsed. This can be
accomplished by having compiler directives and attribute
constructs that control synthesis. Again, this is
reserved for future work.
8) Non-static Variables in Tasks:
The proposed wording of this limitation is, "Variables
declared inside a task are locally static for synthesis
purposes."
9) Bit-Slices in an Event List
It was decided that we will not say anything since
synthesis tools currently are not doing anything
special here relative to the full LRM.