One of the issues discussed at the last 1364.1 WG meeting was whether a new
construct in the upcoming version of the Verilog language (1364-1999)
is needed to support conditional compilation, such as `rtl_synthesis on/off.
The conclusion was that the two mechanisms currently available:
// rtl_synthesis on/off (proposed in 1364.1)
and
`ifdef `fi (already in 1364-1995)
are sufficient for modeling conditional compilation for synthesis purposes.
If you disagree, please explain what kind of new construct you would like
to see in the upcoming Verilog language (1364-1999) to support this.
- bhasker