Subject: Re: Using initialization statements for defining initial setup of registers
From: VhdlCohen@aol.com
Date: Tue Jul 10 2001 - 19:03:22 PDT
In a message dated 7/10/01 11:46:51 AM Pacific Daylight Time,
jbhasker@cadence.com writes:
<> Can you please explain "config_up" reset/ config bit stream? Is this a
> seperate text file that has the initial values for all the FFs that need to
> be read in for simulation? How is reset accomplished when an FPGA is on a
> board?
> >
First off, I am not a Xilinx user. However, I did some Internet research and
came up with the following observations and answers to your question. I am
also posting more questions for discussions.
1. Xilinx uses the attribute INIT.
from page 74: <A HREF="http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap12/lib12006.htm">
http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap12/lib12006.htm>
"INIT initializes ROMs, RAMs, registers, and look-up tables. The least
significant bit of the value corresponds to the value loaded
into the lowest address of the memory element. For register initialization, S
indicates Set and R indicates Reset. The INIT
attribute can be used to specify the initial value directly on the symbol
with the following limitation. INIT may only be used on a
RAM or ROM that is 1 bit wide and not more than 32 bits deep.
Syntax: For ROM, RAM, Registers, LUTs, SRLs:
INIT={value | 1 | 0 | S | R}
where value is a 4-digit or 8-digit hexadecimal number that defines the
initialization string for the memory element, depending on
whether the element is 16-bit or 32-bit. For example, INIT=ABAC1234. If the
INIT attribute is not specified, the RAM is
initialized with zero.
Verilog Example of RAM with initialization, from page 2. NOTE THE INIT
attribute.
<A HREF="http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10073">http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&
getPagePath=10073</A>
module RAM_EXAMPLE (O, A0, A1, A2, A3, D, WE);
output O;
input A0, A1, A2, A3, D, WE;
RAM16X1 U1 (.O(O), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .D(D), .WE(WE));
//synopsys attribute INIT "ABAC"
endmodule
//Verilog Example of ROM
module ROM_EXAMPLE (O, A0, A1, A2, A3);
output O;
input A0, A1, A2, A3;
ROM16X1 U1 (.O(O), .A0(A0), .A1(A1), .A2(A2), .A3(A3));
//synopsys attribute INIT "10A7"
endmodule
2. INIT application and simulation in the Real world.
From newsgroup user: "With block rams (and many other Xilinx primitives), the
block rams
require the INIT generic to be set for simulation, and the attributes
to be set for synthesis. (Don't ask me why, I don't write tools.)
I found the best way to cope with this was to write a wrapper around
the block ram which took the INIT value(s) as a generic, and then
passed these to the block ram as generics (with those horrid translate
on/off pragmas to ensure that the synthesizer doesn't see them), and
also created the attributes. This way, the behavior in simulation
matches the behavior in the downloaded FPGA.
I wrote a function to convert the bit vector (of the generic) to a
string (for the attributes).
In an ideal world, you'd be able to get such a wrapper from the Xilinx
web site. Xilinx Answer 2022 comes closest, but it's still a long
way from the mark. (It only works in synthesis, not in simulation.)"
Bottom line: This attribute solution is a mess! Performing the
initialization in HDL, and having the tool recognize that syntax and deal
with the idiosyncrasies of the target technology.
3. Configuration Method
From Xilinx XC4000E and XC4000X Series Field Programmable Gate Arrays Product
Specification
(used this as an example).
"The devices are customized by loading configuration data into internal
memory cells. The FPGA can either actively
read its configuration data from an external serial or byte-parallel PROM
(master modes), or the configuration
data can be written into the FPGA from an external device (slave and
peripheral modes)."
I believe that this where the initial values of ROMs, RAMs and registers can
be set by the software as per definition in the INIT attribute.
4. Comments and Questions
For FPGAs, synthesis tools produce an EDIF file that is handle by the FPGA
tool vendor to produce the necessary configuration files and configuration
information for the targeted technology. It would seem that a synthesis
vendor could process the initialization information mentioned previously
(with case statement, initial statement, or initial with file). Question:
Would they be willing to comply? How difficult is this? What about
technologies that cannot accomodate such initializations? Is it sufficient
that the synthesizer provides warnings?
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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