Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
From: J. Bhasker (jbhasker@cadence.com)
Date: Tue Oct 23 2001 - 11:50:56 PDT
The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, NOVEMBER 2 from 12:00pm to
1:30pm EASTERN STANDARD TIME.
Call:
USA Toll Free Number: 888-603-9603
USA Toll Number: +1-712-257-3323
PASSCODE: 30096
LEADER: Mr Jayaram Bhasker
Agenda:
1. To continue to discuss RAM and ROM modeling based on his latest
proposal - BenCohen.
2. To review the latest draft D1.7 (posted on our web site): Feedback from
last WG
mtg has not yet been incorporated. However I would like members to review
the draft as
it is present today and post feedback which we can discuss during this
meeting.
Future telecon dates: Dec 7.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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