Subject: Meeting Minutes: Verilog Synthesis Interoperability Working Group Meeting on Nov 2, '01
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Tue Nov 06 2001 - 11:27:28 PST
Meeting minutes: Phone Conference held on Nov 2, '01
----------------------------------------------------
Attendees:
J. Bhasker
Stefen Boyd
Ben Cohen
Cliff Cummings
Sashi Obilisetty
Jenjen Tiao
Joe Wetstein
1. Discussed Cliff's proposal that he had sent out earlier.
2. Cliff proposed to drop the "rtl_" prefix in identifying synthesis
attributes.
Ben seconded. Passed with no one opposing or abstaining.
3. Cliff to add example in 6.1 showing multiple attributes for a single
construct.
To add a note that other kind of attributes can appear, though as a
seperate attribute.
4. Cliff proposed for deprecating metacomments (sec 6.2 of his proposal).
Approved with
no one opposing.
5. Discussed section 6.3 - compiler directives - approved with no
opposition.
6. Add a note in sec 6.3 about transitioning from metacomments to the new
form.
7. Discussed 6.4 - argued that these conditional compilation attributes were
not necessary
given that section 6.3 serves the purpose. Some participants saw a value
in
turning off an individual construct by using just the translate_off
attribute. So this
attribute is to be moved to section 6.1 - to be discussed with the rest
of the
attributes.
8. Sec 6.5 - change warnings to notes as per IEEE standard terminology.
9. Sec 6.6, 6.7, 6.8 - had not synced up with Ben's latest update. The
three attributes are
rom_block, ram_block and logic_block, each with an optional value that is
ignored for
synthesis purposes.
10. Went back to review attributes listed in section 6.1 - there is a need
for someone
to identify what each attribute does/means before further discussion can
proceed. So this
is everyone's action item - IF YOU SEE AN ATTRIBUTE THAT YOU WOULD LIKE
TO SEE
STANDARDIZED, PLEASE PROVIDE A WRITE UP OF ITS SEMANTICS AND USAGE - else
it is
most likely to be removed.
11. Did not get time to discuss Ben's comments on ROM/RAM modeling -
he was requested to post a proposal
so that it could be discussed via email.
Next meetings: Dec 7 2001, Jan 11 2002 (March meeting will be a face-to-face
meeting
during HDLCON conference).
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On Behalf Of J. Bhasker Sent: Tuesday, October 23, 2001 2:51 PM To: vlog-synth@eda.org Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
The next Verilog Synthesis Interoperability Working Group phone conference is scheduled for FRIDAY, NOVEMBER 2 from 12:00pm to 1:30pm EASTERN STANDARD TIME.
Call: USA Toll Free Number: 888-603-9603 USA Toll Number: +1-712-257-3323 PASSCODE: 30096 LEADER: Mr Jayaram Bhasker
Agenda:
1. To continue to discuss RAM and ROM modeling based on his latest proposal - BenCohen.
2. To review the latest draft D1.7 (posted on our web site): Feedback from last WG mtg has not yet been incorporated. However I would like members to review the draft as it is present today and post feedback which we can discuss during this meeting.
Future telecon dates: Dec 7.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com) Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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