Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Thu Nov 01 2001 - 06:06:29 PST
REMINDER! REMINDER! REMINDER!
Additional items on the agenda:
1. To discuss the new "Pragmas" proposal from Cliff.
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On Behalf Of J. Bhasker Sent: Tuesday, October 23, 2001 2:51 PM To: vlog-synth@eda.org Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
The next Verilog Synthesis Interoperability Working Group phone conference is scheduled for FRIDAY, NOVEMBER 2 from 12:00pm to 1:30pm EASTERN STANDARD TIME.
Call: USA Toll Free Number: 888-603-9603 USA Toll Number: +1-712-257-3323 PASSCODE: 30096 LEADER: Mr Jayaram Bhasker
Agenda:
1. To continue to discuss RAM and ROM modeling based on his latest proposal - BenCohen.
2. To review the latest draft D1.7 (posted on our web site): Feedback from last WG mtg has not yet been incorporated. However I would like members to review the draft as it is present today and post feedback which we can discuss during this meeting.
Future telecon dates: Dec 7.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com) Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
This archive was generated by hypermail 2b28 : Thu Nov 01 2001 - 06:13:30 PST