Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01

Subject: Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
From: Paul Graham (pgraham@Cadence.COM)
Date: Wed Oct 24 2001 - 08:28:54 PDT

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• Reply: Clifford E. Cummings: "Attributes & Synthesis Pragmas"
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I'm looking at the set of attributes defined for synthesis. So far, only
full_case and parallel_case are defined. There are lots of synthesis
pragmas supported by Synopsys and Cadence. Why do only two of them appear
as attributes?

Paul

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