Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Wed Oct 24 2001 - 08:52:29 PDT
Paul:
The two you mentioned + three more from Ben Cohen's RAM/ROM modeling
proposal- these are
not yet in the draft.
The WG has discussed attributes/pragmas in the past but could agree on the
only two
listed in the draft. Doug Smith used to the task leader for attributes. If I
remember
right, Don Hejna from Ambit provided the WG with pragmas also for
consideration.
I presume
you can go into past archives (prior to 1999) and dig out the meeting
minutes and
resolutions.
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: Paul Graham [mailto:pgraham] Sent: Wednesday, October 24, 2001 11:29 AM To: jbhasker Cc: vlog-synth@eda.org Subject: Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Nov 2, '01
I'm looking at the set of attributes defined for synthesis. So far, only full_case and parallel_case are defined. There are lots of synthesis pragmas supported by Synopsys and Cadence. Why do only two of them appear as attributes?
Paul
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