Subject: RE: Verilog Synthesis Interoperability Working Group
From: Gilbert Nguyen (nguyen@ibiquity.com)
Date: Fri Aug 10 2001 - 10:56:21 PDT
Sorry folks but due to an unexpected meeting I had to miss the
conference call.
Concerning the 2 items that I have reviewed:
1.Constant function calls: I have sent my concern to the
thread(~7/19/01)
but it seems that the EDA vendors have problems with the
implementation
so we can skip that. Otherwise, I dont have any other concern.
2.Automatic width extension beyond 32 bits: I dont see any problems with
this section. I have paid special attention to the footer for table
4-21 & agree
with the expansion of unknown, tri-state, signed bits & '0' bits.
Regards,
Gilbert Nguyen
iBiquity Digital
908-580-7036
-----Original Message-----
From: Jayaram Bhasker [mailto:jbhasker@cadence.com]
Sent: Monday, August 06, 2001 11:50 AM
To: vlog-synth@eda.org
Subject: Verilog Synthesis Interoperability Working Group Meeting:
Agenda for Aug 10, '01
The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, AUGUST 10 from 12:00pm to 1:30pm
EASTERN STANDARD TIME.
Call:
USA Toll Free Number: 888-391-6578
USA Toll Number: +1-712-257-3711
PASSCODE: 31982
Agenda:
1. To discuss the synthesizability of the new features
of Verilog-2000. Following to report on their assigned items:
- StephenBoyd
- SashiObilisetty
- CliffCummings
- KenCoffman
- GilbertNguyen
- JenjenTiao
- MuzaffarKal
- JoeWetstein : attribute format
It would be nice if you can send your feedback prior to the meeting
so everyone has a chance to review it.
2. To continue to discuss RAM and ROM modeling - BenCohen.
Future telecon dates: Sept 7 (PLEASE NOTE CHANGE!), Oct 5.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312,
jbhasker@cadence.com)
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
This archive was generated by hypermail 2b28 : Fri Aug 10 2001 - 11:02:50 PDT