Subject: 5.4 Modeling three-state drivers
From: VhdlCohen@aol.com
Date: Fri Jun 29 2001 - 11:53:28 PDT
Example 5.19 states that "out will never be driven by three state drivers"
"Example 5.19:
always @ (IN)
begin
TMP = ’bz;
OUT = TMP; // OUT will never be driven by three state drivers.
end "
However, the following code DID produce in Synplify a model driven by a three
state driver.
module tritest (cntrl, outz/*AUTOARG*/) ;
input cntrl;
output outz;
reg tmp;
reg outz;
always @ (cntrl)
begin
tmp = 1'bz;
outz = tmp; // OUT will never be driven by three state drivers.
end
endmodule
From Synplify:
@I::"c:\vhdl_stuff\__dsgn\tritest.v"
Verilog syntax check successful!
Selecting top level module tritest
Synthesizing module tritest
@W:"c:\vhdl_stuff\__dsgn\tritest.v":10:9:10:12|*Output outz has undriven bits
- a simulation mismatch is possible
@W:"c:\vhdl_stuff\__dsgn\tritest.v":2:8:2:12|Input cntrl is unused
@END
@W:"c:\vhdl_stuff\__dsgn\tritest.v":10:9:10:12|tristate driver outz on net
outz has its enable tied to GND
I understand that this is a useless model, but I am questioning the validity
of that example in that section of the spec.
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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