Subject: Re: 5.4 Modeling three-state drivers
From: Ken Coffman (kcoffman@sos.net)
Date: Fri Jul 06 2001 - 08:58:42 PDT
Hi Ben. I think example 5.19 could be explained better. However, I think
your synthesis run proves the point: the 'z' state is not propagated; outz
is tristated, but not because of the input condition. It's tristated
because it doesn't have an input Synplicity recognizes.
At 02:53 PM 6/29/01 -0400, VhdlCohen@aol.com wrote:
>Example 5.19 states that "out will never be driven by three state drivers"
>"Example 5.19:
>always @ (IN)
>begin
> TMP = ’bz;
> OUT = TMP; // OUT will never be driven by three state drivers.
>end "
>
>However, the following code DID produce in Synplify a model driven by a three
>state driver.
>module tritest (cntrl, outz/*AUTOARG*/) ;
> input cntrl;
> output outz;
>
> reg tmp;
> reg outz;
>
> always @ (cntrl)
>begin
> tmp = 1'bz;
> outz = tmp; // OUT will never be driven by three state drivers.
>end
>endmodule
>
> From Synplify:
>@I::"c:\vhdl_stuff\__dsgn\tritest.v"
>Verilog syntax check successful!
>Selecting top level module tritest
>Synthesizing module tritest
>@W:"c:\vhdl_stuff\__dsgn\tritest.v":10:9:10:12|*Output outz has undriven bits
>- a simulation mismatch is possible
>@W:"c:\vhdl_stuff\__dsgn\tritest.v":2:8:2:12|Input cntrl is unused
>@END
>@W:"c:\vhdl_stuff\__dsgn\tritest.v":10:9:10:12|tristate driver outz on net
>outz has its enable tied to GND
>
>I understand that this is a useless model, but I am questioning the validity
>of that example in that section of the spec.
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>* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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