Doug Smith (djsmith@veribest.com) is the task leader for synthesis
directives. Could you please pass on your proposal on the mux inference
directive to him with more details? Thanks,
- bhasker
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From: owner-vlog-synth@vhdl.org (Ed Arthur)
Orig-From: "Ed Arthur" <Ed_Arthur@prominet.com>
To: vlog-synth@eda.org
Date: Wed, 24 Jun 1998 22:35:13 -0400
Subject: Stuff
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Hi,
Firstly, it was nice seeing everyone at the face to face last week.
The rest of you, get moving! :-)
The headline article in this weeks "EE Times" is "EDA integration
finally gets real - Cadence and Synopsys open tool chains". The
article states "...Synopsys offered to license its synthesis constraints
..." and "two years ago, Synopsys offered its RTL (register-transfer
level) synthesis-language subset to the EDA Industry Council".
If the RTL subset is still "up for grabs" does our group have any
purpose? I realize we weren't concerning ourselves with constraints
but it seems like trying to budge the de facto standard is intractable.
Anyhow assuming we still have a purpose, one of the problems I've
seen with Synopsys (at multiple design teams at different companies)
was with the inference of MUXes. An example from a recent ASIC
had an 8-1 Mux which wasn't inferred. Synopsys broke it down to
(mostly) 2-input gates many levels deep. We never got it to
converge so that module ended up with hand instantiation of the entire
datapath and control.
A pragma like "// synthesis mux-recommended" so the tool starts
with a mux implementation or even holds until overridden is what
I'm requesting here.
Thanks,
/Ed
PS: I hope this is the purpose of the list!
--- Edward S. Arthur Enterprise Infrastructure Products Group Data Networking Systems Lucent Technologies 400 Nickerson Road Marlboro, MA 01752 (508) 303-8885 x217 earthur@lucent.com
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